Customizing The Core - Xilinx Zynq-7000 User Manual

Customizing the Core

The 7 series FPGAs QDR II+ SRAM interface solution is customizable to support several
configurations. The specific configuration is defined by Verilog parameters in the top-level
of the core. As per the OOC flow, none of the parameter values are passed down to the user
design RTL file from the example design top RTL file. So, any design related parameter
change is not reflected in the user design logic. The MIG tool should be used to regenerate
a design when parameters need to be changed. These parameters are summarized in
Table 2-12.
Table 2-12: 7 Series FPGAs QDR II+ SRAM Memory Interface Solution Configurable Parameters
Parameter
MEM_TYPE
CLK_PERIOD
BURST_LEN
DATA_WIDTH
BW_WIDTH
NUM_DEVICES
MEM_RD_LATENCY
FIXED_LATENCY_MODE
CPT_CLK_CQ_ONLY
PHY_LATENCY
CLK_STABLE
(1)
IODELAY_GRP
REFCLK_FREQ
RST_ACT_LOW
IBUF_LPWR_MODE
IODELAY_HP_MODE
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Description
This is the memory address bus width
This is the memory clock period (ps).
This is the memory data burst length.
This is the memory data bus width and can be set through
the MIG tool. A maximum
DATA_WIDTH /9
This must be set to
This is the number of memory devices used.
This specifies the number of memory clock cycles of read
latency of the memory device used. This is derived from the
memory vendor data sheet.
This indicates whether or not to use a predefined latency
for a read response from the memory to the client interface.
This indicates only one of the read clocks provided by the
memory (rise clock) is used for the data capture.
This indicates the desired latency through the PHY for a
read from the time the read command is issued until the
read data is returned on the client interface.
This is the number of cycles to wait until the echo clocks are
stable.
This is a unique name for the IODELAY_CTRL that is
provided when multiple IP cores are used in the design.
This is the reference clock frequency for IDELAYCTRLs. This
parameter should not be changed.
This is the active-Low or active-High reset. This is set to 1
when System Reset Polarity option is selected as active-Low
and set to 0 when the option is selected as active-High.
This enables or disables low power mode for the input
buffers.
This enables or disables high-performance mode within the
IODELAY primitive. When set to OFF, the IODELAY operates
in low power mode at the expense of performance.
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Chapter 2: QDR II+ Memory Interface Solution
DATA_WIDTH of 36 is supported.
Options
QDR2PLUS
4
2.0
2.5
0, 1
TRUE
(See memory vendor
data sheet)
200.0
0, 1
ON
OFF
ON
OFF
337
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