Xilinx Zynq-7000 User Manual page 358

a. Browse to the Compiled libraries location and set the path on Compiles libraries
location option.
b. Under the Compilation tab, set the vcs.compile.vlogan.more_options to
-sverilog.
c. Under the Simulation tab, set the vcs.simulate.runtime to 1 ms (there are
simulation RTL directives which stop the simulation after a certain period of time
which is less than 1 ms) as shown in
3. Apply the settings and select OK.
X-Ref Target - Figure 2-53
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Figure
Figure 2-53: Simulation with VCS
Figure 2-51.
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Chapter 2: QDR II+ Memory Interface Solution
2-53.
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