Xilinx Zynq-7000 User Manual page 577

User Interface
The UI is shown in
external memory device.
Table 4-14: User Interface
Signal
app_addr[ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_en
app_rdy
app_hi_pri
app_rd_data
[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_data
[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask
[APP_MASK_WIDTH – 1:0]
app_wdf_rdy
app_wdf_wren
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ui_clk
init_calib_complete
ui_clk_sync_rst
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Table 4-14 and connects to an FPGA user design to allow access to an
Direction Description
Input This input indicates the address for the current request.
Input This input selects the command for the current request.
This is the active-High strobe for the app_addr[], app_cmd[2:0],
Input
and app_hi_pri inputs.
This output indicates that the UI is ready to accept commands.
If the signal is deasserted when app_en is enabled, the current
Output
app_cmd and app_addr must be retried until app_rdy is
asserted.
This active-High input elevates the priority of the current
Input
request.
Output This provides the output data from read commands.
This active-High output indicates that the current clock cycle is
Output
the last cycle of output data on app_rd_data[].
Output This active-High output indicates that app_rd_data[] is valid.
Input This provides the data for write commands.
This active-High input indicates that the current clock cycle is
Input
the last cycle of input data on app_wdf_data[].
Input This provides the mask for app_wdf_data[].
This output indicates that the write data FIFO is ready to receive
Output data. Write data is accepted when app_wdf_rdy = 1'b1 and
app_wdf_wren = 1'b1.
Input This is the active-High strobe for app_wdf_data[].
This active-High input requests that a refresh command be
Input
issued to the DRAM.
This active-High output indicates that the Memory Controller
Output
has sent the requested refresh command to the PHY interface.
This active-High input requests that a ZQ calibration command
Input
be issued to the DRAM.
This active-High output indicates that the Memory Controller
Output has sent the requested ZQ calibration command to the PHY
interface.
Output This UI clock must be a half or quarter of the DRAM clock.
Output PHY asserts init_calib_complete when calibration is finished.
Output This is the active-High UI reset.
www.xilinx.com
577
Send Feedback