Xilinx Zynq-7000 User Manual page 360

3. Apply the settings and select OK.
X-Ref Target - Figure 2-54
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in
5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the
Vivado Design Suite User Guide: Logic Simulation (UG900)
MIG does not generate memory model files for QDR II+ designs. Appropriate memory model
Note:
should be added to the Simulation Sources under Sources window of the Open IP Example Design
project.
For Samsung Memory models appropriate define values should be added to the memory model
itself. Vivado settings does not allow applying define values explicitly on memory models.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
Figure 2-54: Simulation with IES
Figure 2-51.
www.xilinx.com
[Ref 8].
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