Xilinx Zynq-7000 User Manual page 34

• Frequency – This feature indicates the operating frequency for all of the controllers.
The frequency block is limited by factors such as the selected FPGA and device speed
grade.
• PHY to Controller Clock Ratio – This feature determines the ratio of the physical layer
(memory) clock frequency to the controller and user interface clock frequency. The 2:1
ratio lowers the maximum memory interface frequency due to FPGA logic timing
limitations. The user interface data bus width of the 2:1 ratio is four times the width of
the physical memory interface width, while the bus width of the 4:1 ratio is eight times
the physical memory interface width. The 2:1 ratio has lower latency. The 4:1 ratio is
necessary for the highest data rates.
• VCCAUX_IO – Set based on the period/frequency setting. 2.0V is required at the
highest frequency settings in the High Performance column. The MIG tool
automatically selects 2.0V when required. Either 1.8 or 2.0V can be used at lower
frequencies. Groups of banks share the VCCAUX_IO supply. For more information, see
the 7 Series FPGAs SelectIO™ Resources User Guide (UG471)
FPGAs Packaging and Pinout Specification (UG475)
• Memory Type – This feature selects the type of memory parts used in the design.
• Memory Part – This option selects a memory part for the design. Selections can be
made from the list or a new part can be created.
For a complete list of memory parts available, see Answer Record: 54025.
Note:
• Data Width – The data width value can be selected here based on the memory type
selected earlier. The list shows all supported data widths for the selected part. One of
the data widths can be selected. These values are generally multiples of the individual
device data widths. In some cases, the width might not be an exact multiple. For
example, 16 bits is the default data width for x16 components, but eight bits is also a
valid value.
• Data Mask – This option allocates data mask pins when selected. This should be
deselected to deallocate data mask pins and increase pin efficiency. Also, this is
disabled for memory parts that do not support data mask.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
www.xilinx.com
[Ref 2] and the 7 Series
[Ref 3].
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