Xilinx Zynq-7000 User Manual page 567

2. The cmd_seed_i and data_seed_i input values are set for the internal PRBS
generator. This step is not required for other patterns.
3. The instr_mode_i input is set to the desired mode (PRBS is the default).
4. The bl_mode_i input is set to the desired mode (PRBS is the default).
5. The data_mode_i input should have the same value as in the memory pattern
initialization stage detailed in
6. The run_traffic_i input is asserted to start running traffic.
7. If an error occurs during testing (for example, the read data does not match the
expected data), the error bit is set until reset is applied.
8. Upon receiving an error, the error_status bus latches the values defined in
page 563.
With some modifications, the example design can be changed to allow addr_mode_i,
instr_mode_i, and bl_mode_i to be changed dynamically when run_traffic_i is
deasserted. However, after changing the setting, the memory initialization steps need to be
repeated to ensure that the proper pattern is loaded into the memory space.
Note:
When the chip select option is disabled, the simulation test bench always ties the
°
memory model chip select bit(s) to zero for proper operation.
When the data mask option is disabled, the simulation test bench always ties the
°
memory model data mask bit(s) to zero for proper operation.
Setting Up for Simulation
The Xilinx UNISIM library must be mapped into the simulator. The test bench provided with
the example design supports these pre-implementation simulations:
• The test bench, along with vendor's memory model used in the example design
• The RTL files of the Memory Controller and the PHY core, created by the MIG tool
The Questa Advanced Simulator, Vivado Simulator, IES, and VCS simulation tools are used
for verification of the MIG IP core at each software release. Script files to run simulations
with IES and VCS simulators are generated in MIG generated output. Simulations using
Questa Advanced Simulator and Vivado simulators can be done through the Vivado Tcl
Console commands or in the Vivado IDE.
Other simulation tools can be used for MIG IP core simulation but are not specifically
IMPORTANT:
verified by Xilinx.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Memory Initialization.
www.xilinx.com
Table 4-13,
567
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