Xilinx Zynq-7000 User Manual page 480

One way to accomplish the above criteria is to use an external circuit that both
AC-couples and DC-biases the input signals. The figure shows an example circuit for
providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF
provides the 100Ω differential receiver termination because the internal DIFF_TERM
is set to FALSE. To maximize the input noise margin, all RBIAS resistors should be the
same value, essentially creating a VICM level of VCCO/2. Resistors in the 10k to
100 kΩ range are recommended. The typical values for the AC coupling capacitors
CAC are in the range of 100 nF. All components should be placed physically close to
the FPGA inputs.
X-Ref Target - Figure 3-61
LVDS or
LVDS_25
Input Buffer
Figure 3-61: Example Circuit for AC-Coupled and DC-Biased Differential Clock Input
The last set of guidelines on differential LVDS inputs are added within the LVDS and LVDS_25
Note:
(Low Voltage Differential Signaling) section of the 7 Series SelectIO Resources User Guide (UG471)
[Ref 2] in the next release of the document.
These guidelines are irrespective of Package, Column (HR/HP), or I/O Voltage.
Sharing sys_clk between Controllers
MIG 7 series FPGA designs require sys_clk to be in the same I/O bank column as the
memory interface to minimize jitter.
• Interfaces Spanning I/O Columns – A single sys_clk input cannot drive memory
interfaces spanning multiple I/O columns. The input clock input must be in the same
column as the memory interface to drive the PLL using the CMT Backbone, which
minimizes jitter.
• Interfaces in Single I/O Column – If the memory interfaces are entirely contained
within the same I/O column, a common sys_clk can be shared among the interfaces.
The sys_clk can be input on any CCIO in the column where the memory interfaces are
located. This includes CCIO in banks that do not contain the memory interfaces, but
must be in the same column as the memory interfaces.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
V
CCO
FPGA
R
BIAS
R
R = 100Ω
DIFF
R
BIAS
R
www.xilinx.com
Differential Clock
Input to the FPGA
BIAS
C
AC
P
Differential Transmission Line
N
C
AC
BIAS
480
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