Xilinx Zynq-7000 User Manual page 87

5. Vivado invokes VCS and simulations are run in the VCS tool. For more information, see
the Vivado Design Suite User Guide: Logic Simulation (UG900)
Simulation Flow Using IES
1. In the Open IP Example Design Vivado project, under Flow Navigator select
Simulation Settings.
2. Select Target simulator as Incisive Enterprise Simulator (IES).
a. Browse to the Compiled libraries location and set the path on Compiles libraries
location option.
b. Under the Compilation tab, set the ies.compile.ncvlog.more_options to
-sv.
c. Under the Elaboration tab, set the ies.elaborate.ncelab.more_options to
-namemap_mixgen.
d. Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are
simulation RTL directives which stop the simulation after certain period of time
which is less than 1 ms) as shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-50.
www.xilinx.com
[Ref 8].
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