Xilinx Zynq-7000 User Manual page 241

Table 1-74: DDR2/DDR3 Debug Signals (Cont'd)
Signal Name
dbg_wcal_mux_rd_rise0_r
dbg_wcal_mux_rd_fall0_r
dbg_wcal_mux_rd_rise1_r
dbg_wcal_mux_rd_fall1_r
dbg_wcal_mux_rd_rise2_r
dbg_wcal_mux_rd_fall2_r
dbg_wcal_mux_rd_rise3_r
dbg_wcal_mux_rd_fall3_r
dbg_early1_data_match_r
dbg_early2_data_match_r
dbg_wcal_sanity_pat_data_match_valid_r
dbg_prbs_final_dqs_tap_cnt_r
dbg_prbs_first_edge_taps
dbg_prbs_second_edge_taps
dbg_ocal_center_calib_done
dbg_phy_oclkdelay_cal_taps
dbg_ocal_tap_cnt
dbg_bit
dbg_dqs
vio_modify_enable
vio_data_mode_value
vio_addr_mode_value
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Data pattern received on the Write Calibration stage MUX on rising
edge 0.
Data pattern received on the Write Calibration stage MUX on falling
edge 0.
Data pattern received on the Write Calibration stage MUX on rising
edge 1.
Data pattern received on the Write Calibration stage MUX on falling
edge 1.
Data pattern received on the Write Calibration stage MUX on rising
edge 2.
Data pattern received on the Write Calibration stage MUX on falling
edge 2.
Data pattern received on the Write Calibration stage MUX on rising
edge 3.
Data pattern received on the Write Calibration stage MUX on falling
edge 3.
Asserts when the pattern detected is one CK clock cycle early and a
match is found during Write Calibration.
Asserts when the pattern detected is two CK clock cycle early and a
match is found during Write Calibration.
Asserts when the valid pattern is detected on the data and is found to
match with the expected pattern sent during Write Calibration sanity
check.
Tap values set at the end of PRBS Read Leveling stage.
Tap value when the first edge is found during PRBS Read Leveling
stage calibration.
Tap value when the second edge is found during PRBS Read Leveling
stage calibration.
OCLKDELAY center calibration completing indicator.
Final stage 3 tap values for all the bytes in the interface. Bits[5:0] for
byte 0 and Bits[11:6] for byte 1.
Stage 3 tap value during calibration for each group.
VIO Signals (Control)
Currently Unused
Input to select DQS byte for which the ILA displays the tap counts of
PHASER_OUT. For example, set to 4'b0000 to view the results on
DQS[0].
See Table 1-83.
See Table 1-83.
See Table 1-83.
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