Xilinx Zynq-7000 User Manual page 225

Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont'd)
Bank Signal Name
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Byte Group
– C_11
– C_10
– C_09
– C_08
– C_07
– C_06
– C_05
– C_04
– C_03
ODT0 C_02
CKE0 C_01
CS_N0 C_00
RAS_N B_11
CAS_N B_10
WE_N B_09
BA2 B_08
CK_P B_07
CK_N B_06
BA1 B_05
BA0 B_04
A15 B_03
A14 B_02
A13 B_01
A12 B_00
A11 A_11
A10 A_10
A9 A_09
A8 A_08
A7 A_07
A6 A_06
A5 A_05
A4 A_04
A3 A_03
A2 A_02
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I/O Type I/O Number
P 36
N 35
P 34
N 33
P 32
N 31
P 30
N 29
P 28
N 27
P 26
N 25
P 24
N 23
P 22
N 21
P 20
N 19
P 18
N 17
P 16
N 15
P 14
N 13
P 12
N 11
P 10
N 9
P 8
N 7
P 6
N 5
P 4
N 3
Special
Designation
–
–
–
–
DQS-P
DQS-N
–
–
CCIO-P
CCIO-N
CCIO-P
CCIO-N
CCIO-P
CCIO-N
CCIO-P
CCIO-N
DQS-P
DQS-N
–
–
–
–
–
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
225
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