Xilinx Zynq-7000 User Manual page 122

Memory Controller
In the core default configuration, the Memory Controller (MC) resides between the UI block
and the physical layer. This is depicted in
X-Ref Target - Figure 1-53
The Memory Controller is the primary logic block of the memory interface. The Memory
Controller receives requests from the UI and stores them in a logical queue. Requests are
optionally reordered to optimize system throughput and latency.
The Memory Controller block is organized as four main pieces:
• A configurable number of "bank machines"
• A configurable number of "rank machines"
• A column machine
• An arbitration block
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure
Figure 1-53: Memory Controller
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1-53.
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