Xilinx Zynq-7000 User Manual page 292

• Input Clock Period – The desired input clock period is selected from the list. These
values are determined by the chosen memory clock period and the allowable limits of
the PLL parameters. See
PLL parameter limits.
FPGA Options
Figure 2-21 shows the FPGA Options page.
X-Ref Target - Figure 2-21
• System Clock – This option selects the clock type (Single-Ended, Differential or No
Buffer) for the sys_clk signal pair. When the No Buffer option is selected, IBUF
primitives are not instantiated in RTL code and pins are not allocated for the system
clock.
If the designs generated from MIG tool for the No Buffer option are implemented
without performing changes, designs can fail in implementation due to IBUFs not
instantiated for the sys_clk_i signal. So for No Buffer scenarios, sys_clk_i signal
needs to be connected to an internal clock.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
Clocking Architecture, page 322
Figure 2-21: FPGA Options Page
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