Xilinx Zynq-7000 User Manual page 76

Table 1-13: Traffic Generator Signal Descriptions (Cont'd)
Signal
simple_data4[31:0]
simple_data5[31:0]
simple_data6[31:0]
simple_data7[31:0]
fixed_data_i[31:0]
fixed_instr_i[2:0]
fixed_bl_i[5:0]
Memory Initialization and Traffic Test Flow
After power-up, the Init Memory Control block directs the traffic generator to initialize the
memory with the selected data pattern through the memory initialization procedure.
Memory Initialization
1. The data_mode_i input is set to select the data pattern (for example,
data_mode_i[3:0] = 0010 for the address as the data pattern).
2. The start_addr_i input is set to define the lower address boundary.
3. The end_addr_i input is set to define the upper address boundary.
4. The bl_mode_i is set to 01 to get the burst length from the fixed_bl_i input.
5. The fixed_bl_i input is set to either 16 or 32.
6. The instr_mode_i is set to 0001 to get the instruction from the fixed_instr_i
input.
7. The fixed_instr_i input is set to the "WR" command value of the memory device.
8. The addr_mode_i is set to 11 for the sequential address mode to fill up the memory
space.
9. The mode_load_i is asserted for one clock cycle.
When the memory space is initialized with the selected data pattern, the Init Memory
Control block instructs the traffic generator to begin running traffic through the traffic test
flow procedure (by default, the addr_mode_i, instr_mode_i, and bl_mode_i inputs
are set to select PRBS mode).
Traffic Test Flow
1. The addr_mode_i input is set to the desired mode (PRBS is the default).
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Direction Description
Input User-defined simple data 4 for simple 8 repeat data pattern.
Input User-defined simple data 5 for simple 8 repeat data pattern.
Input User-defined simple data 6 for simple 8 repeat data pattern.
Input User-defined simple data 7 for simple 8 repeat data pattern.
Input User-defined fixed data pattern.
User-defined fixed command pattern.
Input 000: Write command
001: Read command
User-defined fixed burst length. Each burst value defines the
Input
number of back to back commands that are generated.
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