Xilinx Zynq-7000 User Manual page 335

Data Alignment and Valid Generation
This phase of calibration:
• Ensures read data from all the read byte groups are aligned to the rising edge of the
ISERDES CLKDIV capture clock
• Sets the latency for fixed-latency mode.
• Matches the latency for each memory when wider memories are derived from small
memories.
• Sends the determined latency to the read valid generation logic.
After the read data capture clock centering is achieved, the calibration logic writes out a
known data pattern to the QDR II+ memory and issues continuous reads back from the
memory. This is done to determine whether the read data comes back aligned to the
positive edge or negative edge of the ICLKDIV output of the PHASER_IN. If the captured
data from a byte group is found aligned to the negative edge, this is then made to align to
the positive edge by using the EDGE_ADV input to the PHASER_IN, which shifts the ICLKDIV
output by one fast clock cycle.
The next stage is to generate the valid signal associated with the data on the client
interface. During this stage of calibration, a single write of a known data pattern is written
to memory and read back. Doing this allows the read logic to count how many cycles elapse
before the expected data returns. The basic flow through this phase is:
1. Count cycles until the read data arrives for each memory device.
2. Determine what value to use as the fixed latency. This value can either be your set
indicated value from the PHY_LATENCY parameter or the maximum latency across all
memory devices.
3. Calibrate the generation of the read valid signal. Using the value determined in the
previous step, delay the read valid signal to align with the read data for user.
4. Assert cal_done.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
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