Xilinx Zynq-7000 User Manual page 490

3. Apply the settings and select OK.
X-Ref Target - Figure 3-68
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in
5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the
Vivado Design Suite User Guide: Logic Simulation (UG900)
For detailed information on setting up Xilinx libraries, see COMPXLIB in the Command Line
Tools User Guide (UG628)
[Ref 18]. For simulator tool support, see the Zynq-7000 AP SoC and 7 Series Devices Memory
Interface Solutions Data Sheet (DS176)
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-68: Simulation with IES
Figure 3-65.
[Ref 17] and the Synthesis and Simulation Design Guide (UG626)
[Ref 1].
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[Ref 8].
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