Xilinx Zynq-7000 User Manual page 512

To measure margin with PRBS8 traffic pattern, set the VIO signals with the listed values in
the traffic_gen_top instance in example_top:
vio_modify_enable = 'd1
vio_data_mode_value = 'd7
vio_addr_mode_value = 'd3
vio_instr_mode_value = 'd4
vio_bl_mode_value = 'd2
vio_fixed_bl_value = 'd128
vio_fixed_instr_value = 'd1
vio_data_mask_gen = 'd0
Next, assert vio_dbg_clear_error or assert system reset before proceeding with
automated margin check. The steps to follow for automated margin check include:
1. Start automated window check by issuing a single pulse on the VIO signal,
dbg_win_start.
2. The VIO signal, dbg_win_active indicates that the automated window check is in
progress. The signals dbg_pi_f_inc and dbg_pi_f_dec must not be used when
dbg_win_active is asserted.
3. The current bit and byte being measured are indicated by the VIO signals,
dbg_win_current_bit and dbg_win_current_byte, respectively.
4. To obtain the left and right tap counts for a completed bit, select the desired bit using
VIO signal, dbg_win_bit_select and observe the results on
dbg_win_left_ram_out and dbg_win_right_ram_out, respectively.
Table 3-33 lists the signals associated with this automated window checking functionality.
Table 3-33: Debug Port Signals
Signal
dbg_win_start
dbg_win_bit_select[6:0]
dbg_win_active
vio_dbg_clear_error
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Description
Single pulse that starts the chk_win state machine. Use the Vivado
logic debug VIO to control this.
Manual bit selection for reporting of results. The results are provided
on dbg_win_left_ram_out and dbg_win_right_ram_out for the bit
indicated.
Flag to indicate chk_win is active and measuring read window margins.
While active, the state machine has control over the debug port
signals.
Clear error control signal controlled by chk_win.
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