Xilinx Zynq-7000 User Manual page 246

Expected Vivado Logic Analyzer Tool Results
X-Ref Target - Figure 1-98
Figure 1-98: Expected Vivado Logic Analyzer Tool Results
Debugging Write Leveling Failures (dbg_wrlvl_err = 1)
Calibration Overview
Write leveling, a new feature in DDR3 SDRAMs, allows the controller to adjust each write
DQS phase independently with respect to the CK forwarded to the DDR3 SDRAM device.
This compensates for the skew between DQS and CK and meets the t
During this stage, the PHY logic asserts the Write_Calib_N input to the PHY Control
block to indicate the start of write leveling. Periodic write requests are issued to the PHY
Control block to generate periodic DQS pulses. The PHASER_IN outputs a free-running clock
to capture the DQ feedback into the DQ IN_FIFOs. The PHASER_OUT fine and coarse taps
are used to phase shift DQS one tap at a time until a 0-to-1 transition is seen on the
feedback DQ.
Write Leveling is performed at three different points during the calibration process. After
memory initialization completes, the PHASER_OUT fine and coarse taps are set to zero.
Write Leveling is then initially performed to align DQS to CK. After OCLKDELAYED
calibration completes, the coarse tap values found during the initial Write Leveling are
carried over and the fine taps are reset to zero. Write Leveling is performed again to ensure
the DQS-to-CK relationship is still correct.
Finally, during Write Calibration both the fine and coarse delays are carried over and final
adjustments are made when necessary. During Write Calibration, the appropriate pattern
must be detected. If Write Leveling aligned DQS to the wrong CK clock, final PHASER_OUT
fine/coarse delay adjustments are required to move DQS up to two CK clock cycles. This
section shows how to capture the Write Leveling results after each of these adjustments.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
www.xilinx.com
specification.
DQSS
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