Xilinx Zynq-7000 User Manual page 416

Here are the rules verified from the input XDC:
• If a pin is allocated to more than one signal, the tool reports an error. Further
verification is not done if the XDC does not adhere to the uniqueness property.
• Verified common rules:
The interface can span across a maximum of three consecutive banks.
°
Interface banks should reside in the same column of the FPGA.
°
Interface banks should be either High Performance (HP) or High Range (HR). HP
°
banks are used for the high frequencies.
The chosen interface banks should have the same SLR region if the chosen device is
°
of stacked silicon interconnect technology.
V I/Os should be used as GPIOs when an internal V
° REF
input and input ports in a bank.
The I/O standard of each signal is verified as per the configuration chosen.
°
The VCCAUX I/O of each signal is verified and provides a warning message if the
°
provided VCCAUX I/O is not valid.
• Verified data pin rules:
Pins related to one strobe set should reside in the same byte group.
°
Write clocks (DK/DK#) should be allocated to the DQS I/O pair.
°
Read clocks (QK/QK#) should be allocated to the MRCC pins for RLDRAM II and
°
should be allocated to DQS I/O pair for RLDRAM 3.
Data (DQ) pins should not be allocated to DQS N pin.
°
An FPGA byte lane should not contain pins related to two different strobe sets.
°
V I/O can be used only when the internal V
° REF
• Verified address pin rules:
Address signals cannot mix with data bytes.
°
It can use any number of isolated byte lanes
°
• Verified system pin rules:
System clock:
°
- These pins should be allocated to either SR/MR CC I/O pair.
- These pins must be allocated in the Memory banks column.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
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is used or if there are no
REF
is chosen.
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is used.
REF
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