Xilinx Zynq-7000 User Manual page 190

Table 1-66: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters (Cont'd)
Parameter
ADDR_MAP
BANK_MAP
CAS_MAP
CKE_MAP
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Bank and byte lane
position information for
the address. 12-bit
parameter provided per
pin.
• [11:8] – Bank position.
Values of 0, 1, or 2 are
supported
• [7:4] – Byte lane position
within a bank. Values of
0, 1, 2, or 3 are
supported.
• [3:0] – Bit position
within a byte lane.
Values of [0, 1, 2, . . ., A,
B] are supported.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Bank and byte lane
position information for
the bank address. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Bank and byte lane
position information for
the CAS command. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Bank and byte lane
position information for
the CKE. This parameter
is referred to as one of
the Address/Control byte
groups. See
ADDR_MAP
description. This
parameter varies based
on the pinout and should
not be changed manually
in generated design.
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Example
Upper-most Data or Address/Control byte group selected bank
is referred to as Bank 0 in parameters notation. Numbering of
banks is 0, 1, and 2 from top to bottom.
Byte groups T0, T1, T2, and T3 are numbered in parameters as
3, 2, 1 and 0, respectively.
Bottom-most pin in a byte group is referred as "0" in MAP
parameters. Numbering is counted from 0 to 9 from
bottom-most pin to top pin with in a byte group by excluding
DQS DQS_N DQS_P
I/Os. and
numbered as A and B, respectively.
192'h000_000_039_038_037_036_035_034_033_032_031_029_0
28_027_026_02B: This parameter is denoted for Address width
of 16 with 12 bits for each pin. In this case the Address width is
14 bits. Ordering of parameters is from MSB to LSB (that is,
ADDR[0] corresponds to the 12 LSBs of the parameter.
12'h02B: Address pin placed in bank 0, byte lane 1, at location B.
12'h235: Address pin placed in bank 2, byte lane 0, at location 5.
See the ADDR_MAP example.
See the ADDR_MAP example.
See the ADDR_MAP example.
pins of the byte group are
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