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Zynq-7000
User Manuals: Xilinx Zynq-7000 Logic Processors
Manuals and User Guides for Xilinx Zynq-7000 Logic Processors. We have
7
Xilinx Zynq-7000 Logic Processors manuals available for free PDF download: User Manual, Design Manual, Getting Started Manual, Application Note, Manual, Quick Start Manual
Xilinx Zynq-7000 User Manual (678 pages)
Memory Interface Solutions
Brand:
Xilinx
| Category:
Processor
| Size: 19 MB
Table of Contents
Introduction
20
Using MIG in the Vivado Design Suite
21
Synplify Pro Black Box Testing
89
Core Architecture
90
Designing with the Core
162
Interfacing to the Core
163
Customizing the Core
180
Design Guidelines
192
Pin Assignments
203
Debugging DDR3/DDR2 Designs
228
Technical Support
229
Introduction
274
Using MIG in the Vivado Design Suite
275
Core Architecture
317
Customizing the Core
337
Design Guidelines
342
Debugging QDR II+ SRAM Designs
351
Introduction
379
Using MIG in the Vivado Design Suite
380
Core Architecture
424
Implementation Details
448
Customizing the Core
458
Design Guidelines
466
Debugging RLDRAM II and RLDRAM 3 Designs
481
Introduction
516
Using MIG in the Vivado Design Suite
517
Core Architecture
575
Designing with the Core
611
Customizing the Core
621
Design Guidelines
631
Introduction
644
Using MIG in the Vivado Design Suite
645
Appendix A: General Memory Routing Guidelines
670
Appendix A: General Memory Routing Guidelines
671
Appendix A: General Memory Routing Guidelines
674
Appendix A: General Memory Routing Guidelines
675
Appendix A: General Memory Routing Guidelines
676
Xilinx Resources
677
Please Read: Important Legal Notices
678
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Xilinx Zynq-7000 Design Manual (78 pages)
All Programmable SoC PCB
Brand:
Xilinx
| Category:
Controller
| Size: 2 MB
Table of Contents
Revision History
2
Table of Contents
4
Chapter 1: Introduction
6
About this Guide
6
Additional Support Resources
6
PCB Structures
7
Chapter 2: PCB Technology Basics
7
Introduction
7
Traces
8
Planes
8
Vias
8
Pads and Antipads
8
Lands
9
Dimensions
9
Transmission Lines
10
Return Currents
11
PCB Decoupling Capacitors
12
Recommended PCB Capacitors Per Device
12
Chapter 3: Power Distribution System
12
Introduction
12
Required PCB Capacitor Quantities
13
Required PCB Capacitor Quantities Per Device (PL)
13
Required PCB Capacitor Quantities Per Device (PS)
14
Capacitor Specifications
15
PCB Capacitor Specifications
15
PCB Bulk Capacitors
16
PCB Capacitor Placement and Mounting Techniques
16
PCB High-Frequency Capacitors
16
MID and High Frequency Capacitors
16
Basic PDS Principles
17
Noise Limits
17
Example Capacitor Land and Mounting Geometries
17
Role of Inductance
19
Simplified PDS Circuit
19
Further Simplified PDS Circuit
19
Capacitor Parasitic Inductance
20
Parasitics of a Real, Non-Ideal Capacitor
21
Contribution of Parasitics to Total Impedance Characteristics
21
PCB Current Path Inductance
22
Capacitor Mounting Inductance
22
Effective Frequency Example
22
Example Cutaway View of PCB with Capacitor Mounting
23
Plane Inductance
24
Power-Ground Plane Sandwiches
24
AP Soc Mounting Inductance
25
To Reduce Parasitic Inductance
25
PCB Stackup and Layer Order
26
Capacitor Effective Frequency
26
Capacitor Anti-Resonance
28
Capacitor Placement Background
29
Stabilization Capacitors
30
Power Supply Consolidation
30
Simulation Methods
31
EDA Tools for PDS Design and Simulation
31
PDS Measurements
32
Noise Magnitude Measurement
32
Noise Spectrum Measurements
34
Infinite Persistence Measurement of same Supply
34
Optimum Decoupling Network Design
36
Troubleshooting
37
Excessive Noise from Other Devices on the PCB
37
Parasitic Inductance of Planes, Vias, or Connecting Traces
37
I/O Signals in PCB Are Stronger than Necessary
38
I/O Signal Return Current Traveling in Sub-Optimal Paths
38
Interface Types
39
Single-Ended Versus Differential Interfaces
39
Chapter 4: Selectio Signaling
39
Introduction
39
SDR Versus DDR Interfaces
40
Single-Ended Signaling
40
Modes and Attributes
40
Input Thresholds
41
Topographies and Termination
41
Unidirectional Topographies and Termination
42
Unidirectional Point-To-Point Topographies
42
Parallel-Terminated Unidirectional, Point-To-Point Topography
42
Series-Terminated Unidirectional, Point-To-Point Topography
43
“Weak Driver” Unidirectional, Point-To-Point Topography
43
Thevenin Parallel Termination
44
Unidirectional Multi-Drop Topographies
45
Basic Multi-Drop Topography
46
Bidirectional Topography and Termination
46
Bidirectional Point-To-Point Topographies
47
Parallel Terminated Bidirectional Point-To-Point Topography
47
“Weak Driver” Bidirectional Point-To-Point Topography
48
Bidirectional Multi-Point Topographies
50
Main Power Supplies
51
Power Domains
51
Chapter 5: Processing System (PS) Power and Signaling
51
Filtering Circuit Layout
53
PS DDR Interface I/O Supply
53
PS DDR Power Supplies
53
PS MIO Power Supplies
54
PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination Voltage
54
Unused DDR Memory
54
Power Sequencing
55
Power Supply Ramp Requirements
55
PS_MIO_VREF – RGMII Reference Voltage
55
Voltage Mode Configuration
55
Boot Mode Pin MIO[8]
56
PS Clock and Reset
56
PS_CLK – Processor Clock
56
PS_POR_B – Power on Reset
56
DDR Interface Signal Pins
57
Dynamic Memory
57
Setting Mode Pins
57
DDR Unused Pins
58
Dynamic Memory Implementation
58
DDR3/3L Board Implementation
59
DDR2 Board Implementation
60
DDR Supply Voltages
61
DDR Voltage
61
LPDDR2 Board Implementation
61
DDR Max Trace Length
62
DDR Termination
62
DDR Trace Length
62
DDR Delay Match
63
DDR Routing Topology
63
DDR Trace Impedance
63
Ddr Zq
63
CAN (Controller Area Network)
65
Ethernet GEM
65
IIC
65
MIO/EMIO IP Layout Guidelines
65
Temperature Sensing Diodes
66
Trace Port Interface Unit (TPIU)
66
Uart
66
Usb Ulpi
66
Maximum Operating Frequency (Feedback Mode Enabled)
67
Qspi
67
Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices
69
Chapter 6 : Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices
69
Introduction
69
Functional and Performance Differences
70
Package Differences
70
Transceiver Differences
70
PCB Layout Considerations
70
Software Considerations
71
Xilinx Resources
72
Product Support and Documentation
72
Appendix A: Additional Resources and Legal Notices
72
PL Documents – Device and Boards
73
References
73
Solution Centers
73
Zynq-7000 AP Soc Documents
73
Advanced Extensible Interface (AXI) Documents
74
Design Tool Documents
74
Git Information
74
Software Documents
74
Chipscope Pro Documentation
75
Xilinx Embedded Development Kit (EDK)
75
Xilinx ISE Design Suite
75
Xilinx Problem Solvers
75
Please Read: Important Legal Notices
76
Xilinx Zynq-7000 User Manual (70 pages)
Brand:
Xilinx
| Category:
Motherboard
| Size: 0 MB
Table of Contents
Revision History
3
Table of Contents
6
Chapter 1: Introduction
8
The Base Targeted AP Soc Reference Design
8
Base TRD Key Features
11
Chapter 2: Functional Description
14
Hardware Architecture
14
Software Architecture
31
Appendix A: Register Description
46
Sobel Filter Registers
46
Appendix B: Extended Display Identification Data
55
Storing and Programming EDID Data
55
Appendix C: Directory Structure
56
Included Files and Systems
56
Appendix D: Petalinux Software Development Kit
58
Getting Started with the Petalinux SDK
59
Install the Xilinx Vivado Design Suite
64
Set up Git Tools
64
Appendix F: Additional Resources
65
Xilinx Resources
65
Solution Centers
65
References
65
Appendix G: Regulatory and Compliance Information
68
Declaration of Conformity
68
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Xilinx Zynq-7000 Getting Started Manual (50 pages)
All Programmable SoC, Evaluation Kit and Video and Imaging Kit, Vivado Design Suite 2013.3
Brand:
Xilinx
| Category:
Motherboard
| Size: 13 MB
Table of Contents
Revision History
3
Table of Contents
5
Chapter 1: Introduction
7
Overview
7
ZC702 Evaluation Kit Contents
8
Zynq-7000 AP Soc Video and Imaging Kit Contents
10
Key Features of the ZVIK
10
Default Jumper and Switch Settings
11
Chapter 2: ZC702 Evaluation Kit Built-In Self-Test
15
Introduction
15
BIST Setup Requirements
15
Hardware bist Board Setup
16
Hardware Bring-Up
17
Run the bist Application
22
Chapter 3: Getting Started with the Base Targeted Reference Design
25
Introduction
25
Base TRD Key Features
27
Base TRD Hardware Setup Requirements
28
TRD Demonstration Procedure
30
Running the Qt-Based GUI Application Demonstration
32
Running the UART Menu-Based Demonstration Application
36
Running the Video Demonstration for 720P Video Resolution
38
Chapter 4: Using the AMS101 Evaluation Card
41
Introduction
41
Requirements to Get Started
42
Evaluating AMS
43
Chapter 5: Next Steps
45
Next Steps for the Zynq-7000 AP Soc Video and Imaging Kit (ZVIK)
45
Xilinx Zynq-7000 Application Note (15 pages)
Programmable SoC
Brand:
Xilinx
| Category:
Motherboard
| Size: 0 MB
Table of Contents
Hardware and Software Requirements
4
Reference System Description
5
Hardware Root of Trust
7
Measured Boot
8
Integrity Measurement Architecture
9
Trusted Platform Module
10
Zynq 7000 Soc-TPM Interface
11
Network Security in Measured Boot
12
Reference Design Functional Overview
13
Revision History
14
Please Read: Important Legal Notices
14
Xilinx Zynq-7000 Manual (8 pages)
Brand:
Xilinx
| Category:
Computer Hardware
| Size: 0 MB
Xilinx Zynq-7000 Quick Start Manual (4 pages)
All Programmable SoC Evaluation Kit
Brand:
Xilinx
| Category:
Motherboard
| Size: 1 MB
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