Xilinx Zynq-7000 User Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Motherboard
  5. Zynq-7000
  6. User manual
Xilinx Zynq-7000 User Manual

Xilinx Zynq-7000 User Manual

Hide thumbs Also See for Zynq-7000:
Table of Contents

Advertisement

Quick Links

Zynq-7000
All Programmable SoC ZC702
Base Targeted Reference Design
(Vivado Design Suite 2013.3)
User Guide
UG925 (v6.0) February 21, 2014
This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4
This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4
This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4
This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4

Advertisement

Table of Contents
loading

Related Manuals for Xilinx Zynq-7000

Summary of Contents for Xilinx Zynq-7000

  • Page 1 Zynq-7000 All Programmable SoC ZC702 Base Targeted Reference Design (Vivado Design Suite 2013.3) User Guide UG925 (v6.0) February 21, 2014 This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4 This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4 This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4...
  • Page 2 Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Revision History

    Product Guide and PG014, LogiCORE IP YCrCb to RGB Color-Space Converter Product Guide were added to references. Appendix G, Regulatory and Compliance Information was added. Appendix H, Warranty was added. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com UG925 (v6.0) February 21, 2014...
  • Page 4 Video Multiplexer, page 26 added the final sentence “For detailed information ...” The dvi2axi section on page 25 was removed. Figure 2-4 changed “Xilinx DMA” block to “Xilinx AXI VDMA.” Table 2-9 changed “core DMA” to “Xilinx AXI VDMA.” XVDMA Driver, page 35 changed “Xilinx DMA”...
  • Page 5 Table C-1. Added Appendix D, PetaLinux Software Development Kit. Revised Appendix F, Additional Resources to conform to the board and kit document reference and style format du jour. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com UG925 (v6.0) February 21, 2014...

  • Page 6: Table Of Contents

    Install the Xilinx Vivado Design Suite ........
  • Page 7 Markings ............... . 69 Appendix H: Warranty Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...

  • Page 8: Chapter 1: Introduction

    (PL), Base TRD package directory structure, and pointers to enable the user to further develop embedded platforms based on Zynq-7000 AP SoC architecture. To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base Targeted Reference Design webpage wiki.xilinx.com/zc702-base-trd.
  • Page 9 ARM Cortex-A9 cores. The software application works in tandem with hardware and provides the user the choice of offloading computation-intensive processing to the PL-based hardware subsystem. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 10 Imaging Kit M_AXI3_GP 32 bit UG925_c1_01_061913 Figure 1-1: Zynq-7000 AP SoC Base TRD System Block Diagram The TRD deliverables include source code for RTL design and software packages such as the Linux OS, device drivers, the application, and the GUI.

  • Page 11: Base Trd Key Features

    A Sobel accelerator • AXI Performance Monitor Base TRD software includes: • Xilinx Zynq-7000 standard Linux kernel (based on Open Source Linux 3.x) • Linux device drivers for TRD-specific IPs • Qt-based Linux application demonstrating the video processing pipeline List of Acronyms Table 1-1 lists acronyms used in this document.
  • Page 12 Intellectual property JTAG Joint Test Action Group KFLOPS Kilo floating-point operations per second Nonvolatile memory On-chip memory Operating system Programmable logic (inside the Zynq-7000 AP SoC) Processing system Read only Register transfer level Read/write Self clear Secure Digital SD MMC...
  • Page 13 Xilinx Platform Studio ZC702 Platform development board based on the Zynq AP SoC Z-7020 device Zynq Z-7020 An implementation of the Zynq-7000 AP SoC with a fixed feature set and PL capabilities Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...

  • Page 14: Chapter 2: Functional Description

    It also describes how data flows through the various connected IPs and includes information about the flow of application control. To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base Targeted Reference Design wiki page wiki.xilinx.com/zc702-base-trd.
  • Page 15 Interface Video HDMI_IN CRESAMPLE_0 VID_IN_AXI4S TPG_0 Video Sync Signals 1080p Video Monitor 1080p VIDEO_MUX_0 VTC_0 UG925_c2_01_020514 Figure 2-1: Zynq-7000 AP SoC Base TRD Hardware Block Diagram Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 16 1. The figures provided here are only indicative of nature and can vary between different tool chain versions. The PL-implemented video IP and custom logic address map is shown in Table 2-2. Table 2-2: FPGA Logic Address Map for the Zynq-7000 AP SoC ZC702 Base TRD Instance Peripheral Base Address...
  • Page 17 This section describes some of the features of the PS used in this design. For detailed information about the complete feature set including a functional description, see the Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) [Ref The APU includes the dual ARM Cortex-A9 core processor, snoop control unit (SCU), L2 cache controller, on-chip memory (OCM), 8-channel DMA, system watchdog timer (SWDT), and triple-timer controller (TTC) blocks.
  • Page 18 Hardware Architecture IPs provided by Xilinx are AXI4-compliant, and the soft AXI interconnect IP provides protocol bridging as needed. S_AXI_HP - The high performance slave AXI interfaces (S_AXI_HP) connect the PL to AFI blocks in the PS. The PL has four AXI masters out of which two are connected to the S_AXI_HP0 port and two are connected to the S_AXI_HP2 port.
  • Page 19 BUFGMUX dynamically selects which video clock source drives logic running on the video clock domain. The VTC, VID_IN_AXI4S, and logiCVC-ML blocks run on the video clock. Table 2-5 lists system clocks. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 20 • video_clk_2 148.5 fmc_imageon_hdmi_in_0_clk_pin • video_clk 148.5 video_clk_int Processor ps7_0 • FCLK_CLK0 FPGA_CLK • M_AXI_GP0_ACLK clk_75mhz • S_AXI_HP0_ACLK clk_150mhz • S_AXI_HP2_ACLK clk_150mhz Buses axi4_0 • INTERCONNECT_ACLK clk_150mhz Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 21 • Clk clk_75mhz TPG_VDMA • m_axi_s2mm_aclk clk_150mhz • s_axi_lite_aclk clk_75mhz • s_axis_s2mm_aclk clk_150mhz PERF_MON_HP0_HP2 • SLOT_0_AXI_ACLK clk_150mhz • SLOT_1_AXI_ACLK clk_150mhz • S_AXI_ACLK clk_75mhz • CORE_ACLK clk_150mhz VTC_0 Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 22 (PG164) [Ref AXI Interconnect Instances: system_top_i/axi4_hp0, system_top_i/axi4_hp2, system_top_i/axi4_gp0 FPGA logic design has two interconnects for AXI memory-mapped masters and one interconnect for the AXI register interface. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 23 The AXI register interface is clocked at 75 . The Zynq-7000 AP SoC PS GP0 port acts as master on this interconnect and connected slaves have register maps. AXI TPG and VTC are examples of slaves connected to this interconnect.
  • Page 24 The box size register controls the size of the box, and the color of the box is selected by the box color register. The width Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 25 Instance: system_top_i/HDMI_IN This IP core receives video from FMC-IMAGEON, in YCrCb 4:2:2 format, with embedded vblank and hblank signals, and extracts blanking information. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 26 Start register is written through the Sobel interface. The Sobel filter detects the edge in the video frame and the processed frame is sent out on AXI stream interface. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 27 PS I2C controllers are used as bus masters to configure a number of I2C slaves or clients. The bus hierarchy is shown in Figure 2-2. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 28 PL. The same clock is used not only to drive the display output, but it also connects to the VTC's timing generator which in turn provides video timing signals to the TPG. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 29 Note that more complex ICs like the ADV7511 or the ADV7611 can also have internal I2C bus structures to communicate with sub-components (e.g., the ADV7611 is comprised of 7 I2C sub-devices with the EDID EEPROM being one of them). Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 30 It also exposes all the memory accesses required to complete the computation as fast as possible. In this case, achieving maximum performance requires nine read operations to the memory storing the input image to construct the 3 x 3 window on which Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...

  • Page 31: Software Architecture

    The code in the TRD has been modified to express tiered memory architecture to meet the performance requirements of the design. Software Architecture This section explains the software architecture for the Zynq-7000 AP SoC ZC702 Base TRD. Figure 2-4 illustrates a top-level view of the software architecture.
  • Page 32 NAND/NOR flashes are not available on the ZC702 board. This TRD uses SD card boot mode for booting. For details on pin and jumper configuration for SD boot, see the Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com...
  • Page 33 The Xilinx Linux kernel is based on the mainline open source kernel Git tree, adding support for a variety of Xilinx IP core drivers and reference boards. The source code is available on the Xilinx Open Source ARM Git Repository: https://github.com/xilinx.
  • Page 34 Software Architecture The Xilinx Linux kernel is extended (patched) to support functionality specific to the Base TRD. Patching and building the Linux kernel is explained in the Zynq-7000 Base Targeted Reference Design wiki page at wiki.xilinx.com/zc702-base-trd. Table 2-9 lists kernel drivers used for the Base TRD.
  • Page 35 XVDMA Driver XVDMA is a character driver used for configuring and controlling video DMA transactions for both TPG and Sobel hardware. XVDMA internally calls the Xilinx AXI VDMA driver to complete the task and interrupt handling. The device node that uses the XVDMA driver is /dev/xvdma. The following IOCTLs are defined for the XVDMA driver and contain the corresponding IOCTL arguments to be used: •...
  • Page 36 Control operations supported - Only s_cntrl is supported to set a new control value. V4L2 I2C sub-devices and operations support -Table 2-10 shows driver operations support for sub-devices. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 37 Support for Alpha blending and Color keyed transparency. • Pixel, Layer or Color lookup table alpha blending mode. • Programmable layer memory base address and stride. • Double/triple buffering enables flicker-free reproduction. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 38 Xylon FB driver. Table 2-12: Custom IOCTL Calls for the Xylon FB Driver Sr. No. System Call XYLONFB_GET_LAYER_IDX XYLONFB_GET_LAYER_ALPHA XYLONFB_SET_LAYER_ALPHA XYLONFB_LAYER_COLOR_TRANSP XYLONFB_GET_LAYER_COLOR_TRANSP XYLONFB_SET_LAYER_COLOR_TRANSP XYLONFB_GET_LAYER_SIZE_POS XYLONFB_SET_LAYER_SIZE_POS Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 39 Number of logiCVC layer which uses RGBA format active-layer Ordinal number of logiCVC layer which is used for system console videomode Display resolution for which logiCVC will be initialized in HRESxVRES text format Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 40 At run time, the kernel assigns one of the cores for software Sobel filter processing and other core for running the rest of the application and the operating system. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 41 MAX GUI mode. All other controls are available in both the MAX and MIN GUI mode. X-Ref Target - Figure 2-7 UG925_c2_07_011014 Figure 2-7: Minimized GUI Mode Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 42 VDMA (using the XVDMA driver) • VDMA reset and multiplexer switching for external video (using the GPIO driver) • logiCVC-ML control (using the frame buffer driver) Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 43 DDR memory (using VDMA), detects the edge, and writes the filtered image in the reserved video memory in DDR (using VDMA). The display controller displays video memory (filtered TPG pattern). Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 44 The algorithm takes the RGB raw formatted image and detects the image object’s edges based on the pixel luminance values. Input : ZNQ_S32 *rgb_data_in Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 45 The implemented algorithm computes each output pixel's value of the frame using the Sobel filter edge detection algorithm. This function returns a 32-bit edge-detected ARGB array of the frame with each color as 8-bit depth. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...

  • Page 46: Appendix A: Register Description

    RW/SC Start processing the frame. Global Interrupt Enable Register The relative address of the Global Interrupt Enable register is 0x04. Table A-2 describes this register's structure. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 47 Frame processing done interrupt status. Number of Rows Register The relative address of the Number of Rows register is 0x14. Table A-5 describes this register's structure. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 48 XR0C0 coefficient for Sobel filtering. XR0C1 Coefficient Register The relative address of the XR0C1 Coefficient Register is 0x2C. Table A-8 describes this register's structure. Relative address 0x2C Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 49 Table A-11 describes this register's structure. Relative address 0x44 Table A-11: XR1C1 Coefficient Register Bit Position Mode Default Value Description 31:0 XR1C1 coefficient for Sobel filtering. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 50 Description 31:0 XR2C1 coefficient for Sobel filtering. XR2C2 Coefficient Register The relative address of the XR2C2 Coefficient Register is 0x64. Table A-15 describes this register's structure. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 51 YR0C1 coefficient for Sobel filtering. YR0C2 Coefficient Register The relative address of the YR0C2 Coefficient Register is 0x7C. Table A-18 describes this register's structure. Relative address 0x7C Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 52 Table A-21 describes this register's structure. Relative address 0x94 Table A-21: YR1C2 Coefficient Register Bit Position Mode Default Value Description 31:0 YR1C2 coefficient for Sobel filtering. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 53 Description 31:0 YR2C2 coefficient for Sobel filtering. High Threshold Register The relative address of the High Threshold register is 0xB4. Table A-25 describes this register's structure. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 54 Table A-27 describes this register's structure. Relative address 0xC4 Table A-27: Invert Output Register Bit Position Mode Default Value Description 31:1 Reserved. Inverts output of Sobel filter. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...

  • Page 55: Appendix B: Extended Display Identification Data

    This EDID data is read by the video source, and video is output accordingly by the source. Contents of EDID data can be modified by the ADVANTIV EDID editor: http://ez.analog.com/docs/DOC-2143 Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...

  • Page 56: Appendix C: Directory Structure

    X-Ref Target - Figure C-1 zc702-zvik-base-trd-rdf0286 ready_to_test hardware software BOOT.bin vivado petalinux lgpl-2.1.txt image.ub vivado_hls patch README.txt workspace autostart.sh UG927_aC_01_011514 Figure C-1: Directory Structure Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 57 Included Files and Systems Table C-1: Explanation of Directories in the Zynq-7000 AP SoC ZC702 Base TRD File System Directory Purpose This directory contains the documents provided with the Zynq-7000 AP SoC ZC702 Base TRD, including this user guide. This directory contains a pre-built hardware design and software executables which ready_to_test provide a quick way to run the video demonstration.

  • Page 58: Appendix D: Petalinux Software Development Kit

    Easily propagate user applications to embedded Linux systems using Zynq-7000 devices • Test a Linux system based on a Zynq-7000 device in a virtual machine environment using QEMU. The PetaLinux SDK will automatically generate a custom, Linux board support package (BSP) including device drivers for Xilinx embedded processing IP cores, kernel and boot loader configurations.

  • Page 59: Getting Started With The Petalinux Sdk

    JTAG. The PetaLinux SDK complements use of the Xilinx SDK by allowing application developers to continue using the Xilinx SDK to build and deploy against any Linux system that is configured with the PetaLinux SDK tools. Getting Started with the PetaLinux SDK The PetaLinux SDK provides tools to create project, user application, libraries, modules, and templates for either C or C++ based templates.
  • Page 60 Getting Started with the PetaLinux SDK BOOT.bin BOOT.bin is a boot image generated using PetaLinux tools. It includes Xilinx first stage bootloader, FPGA bitstream and u-boot. image.ub image.ub is a multi-component FIT binary including the linux kernel, devicetree and root filesystem.
  • Page 61 Specify the path to the root file system. root= /path/to/filesystem • Configures IP addresses of devices and also how to set up the IP routing table ip=<client-ip>:<server-ip>:<gatewayip>:<netmask>:<hostname>: Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 62 Force usage of a specific amount of memory to the kernel, Kernel now is not able to see the whole system memory. In Zynq the [total memory] - [kernel memory] is used as video memory. mem=<memory for kernel> Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 63 Getting Started with the PetaLinux SDK The Zynq Base TRD uses latest Xilinx Open Source Linux (OSL) kernel, not the default IMPORTANT: PetaLinux Linux kernel that comes as a part of PetaLinux SDK. See the documents listed here for more information: •...

  • Page 64: Install The Xilinx Vivado Design Suite

    Install the Zynq-7000 AP SoC Design and Development Environment Install the Xilinx Vivado Design Suite The user needs to install the Embedded Edition and System Edition of the Xilinx Vivado Design Suite. See Vivado Design Suite User Guide: Release Notes, Installation (UG973) [Ref 17] to install and license the Vivado Design Suite.

  • Page 65: Appendix F: Additional Resources

    ZC702 Evaluation Kit Master Answer Record (AR 47864) These Xilinx documents and sites provide supplemental material useful with this guide: 1. Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide (UG926) 2. Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) 3.
  • Page 66 18. Zynq-7000 All Programmable SoC Software Developers Guide (UG821) 19. Xilinx Design Tools: Installation and Licensing Guide (UG798) 20. Zynq-7000 All Programmable SoC: Concepts, Tools, and Techniques Guide (UG873) 21. Quick Front-to-Back Overview Tutorial: PlanAhead Design Tool (UG673) 22. Zynq-7000 All Programmable SoC Overview (DS190) 23.
  • Page 67 AMBA AXI4-stream protocol specification PCI-SIG PCI Express specifications Silicon Labs Si570, Si5324C, CP2103GM, USB to UART Bridge, VCP Drivers Northwest Logic PCI Express® Solution, DMA Back End Core Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...

  • Page 68: Appendix G: Regulatory And Compliance Information

    Methods of Measurement This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback...
  • Page 69 This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. Zynq-7000 AP SoC ZC702 Base TRD www.xilinx.com Send Feedback UG925 (v6.0) February 21, 2014...
  • Page 70 Customer. For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products.

Table of Contents