Xilinx Zynq-7000 User Manual page 463

Table 3-15: RLDRAM II Memory Interface Solution Pinout Parameters (Cont'd)
Parameter Description
Three fields, one per possible I/O
bank. 12-bit parameter per byte lane
used to determine which I/O
locations are used to generate the
necessary PHY structures. This
parameter is provided per bank.
PHY_0_BITLANES,
Except for the CK_P/CK_N,
PHY_1_BITLANES,
DK_P/DK_N, QK_P/QK_N, and all Data
PHY_2_BITLANES
and Address/Control pins are
considered for this parameter
generation.
This parameter varies based on the
pinout and should not be changed
manually in generated design.
Bank and byte lane position
information for the chip select. 12-bit
parameter provided per pin.
• [3:0] – Bit position within a byte
• [7:4] – Byte lane position within a
CK_MAP
• [11:8] – Bank position. Values of 0,
This parameter varies based on the
pinout and should not be changed
manually in generated design.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
lane. Values of [0, 1, 2, . . ., A, B] are
supported.
bank. Values of 0, 1, 2, or 3 are
supported.
1, or 2 are supported
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Example
This parameter is denoted for all byte groups of a
selected bank. All 12 bits are denoted for a byte
lane and are ordered from MSB:LSB as
BA98_7654_3210. For example, this parameter is
48'hFFE_FFF_000_ DF6 for one bank.
12'hBFC (12'b1011_1111_1100) = bit lanes 0, 1,
and 10 are not used, all others are used.
Upper-most Data or Address/Control byte group
selected bank is referred to as Bank 0 in
parameters notation. Numbering of banks is 0, 1,
and 2 from top to bottom.
Byte groups T0, T1, T2, and T3 are numbered in
parameters as 3, 2, 1, and 0 respectively.
Bottom-most pin in a byte group is referred to as
"0" in MAP parameters. Numbering is counted
from 0 to 9 from the bottom-most pin to the top
pin within a byte group by excluding DQS I/Os.
DQS_N and DQS_P pins of byte group are
numbered as A and B, respectively.
144'h000_000_000_000_000_000_000_000_000_00
0_235_11B = This parameter is denoted for clock
width of 12 with 12 bits for each pin. In this case,
the clock width is 2 bits. Ordering of parameters is
from MSB to LSB (that is, CK[0] corresponds to the
12 LSBs of the parameter).
12'h11B = CK[0] placed in bank 1, byte lane 1, at
location A.
12'h235 = CK[1] select placed in bank 2, byte lane
3, at location 5.
Only the CK_P location is denoted, with the CK_N
located on the corresponding N-side location of
an I/O pin pair.
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