Xilinx Zynq-7000 User Manual page 255

Table 1-79: Debug Signals of Interest for Write Calibration (Cont'd)
Signal Name
dbg_wcal_mux_rd_fall1_r
dbg_wcal_mux_rd_rise2_r Data pattern received on rising edge 2.
dbg_wcal_mux_rd_fall2_r
dbg_wcal_mux_rd_rise3_r Data pattern received on rising edge 3.
dbg_wcal_mux_rd_fall3_r
1. The number on wrcal_dqs_cnt when dbg_wrcal_err asserts signifies the byte that
failed write calibration. Debug should be focused on this byte group.
2. Observe the rddata bus or the mux_rd_fall/riseX_r buses and look for the
appropriate data pattern. Note, mux_rd_fall/rise_2/3_r is not used with the
half-rate controller and it is always zero. Again, the three scenarios that allow write
calibration to continue are:
On-time write expected pattern – FF00AA5555AA9966
°
One cycle early write expected pattern – AA5555AA9966BB11
°
Two cycles early expected pattern – 55AA9966BB11EE44
°
3. If none of these three patterns are observed on a failing byte, look at the failing pattern
and determine how the pattern is failing. Look if there are failing DQ bit(s) within a byte,
failing bytes, and others. If the late write pattern noted above was detected, there is
most likely a trace length issue between DQS and CK where CK is not longer than DQS as
required.
4. If the design is stuck in the Write Calibration stage, the issue could be related to either
the write or the read. Determining whether the write or read is causing the failure is
critical. The following steps should be completed using dbg_wrcal_start as the
scope trigger. To perform this, dbg_wrcal_start must be brought out to an I/O. For
additional details and example Read and Write scope shots, review the
Data Error is Due to the Write or
a. To ensure the writes are correct, observe the write DQS to write DQ relationship at the
memory using high quality scope and probes. During write calibration, a write is
followed by a read so care needs to be taken to ensure the write is captured. See the
Determining If a Data Error is Due to the Write or Read
a failing bit, determining the write DQS to write DQ relationship for the specific DQ bit
is critical. The write ideally has the DQS center aligned in the DQ window.
Misalignment between DQS and DQ during Write Calibration points to an issue with
OCLKDELAY calibration. Review the
section.
b. If the DQ-DQS alignment looks correct, next observe the WE_N to DQS relationship at
the memory during a write again using high quality scope and probes. The WE_N to
DQS delay must equal the CAS Write Latency (CWL).
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Data pattern received on falling edge 1.
Data pattern received on falling edge 2.
Data pattern received on falling edge 3.
Read.
www.xilinx.com
section for details. If there is
Debugging OCLKDELAYED Calibration Failures
Determining If a
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