Xilinx Zynq-7000 User Manual page 623

Table 4-25: 7 Series FPGA Memory Solution Configuration Parameters (Cont'd)
Parameter
DQ_WIDTH
DQS_WIDTH
BURST_MODE
BM_CNT_WIDTH
ADDR_CMD_MODE
(3)
ORDERING
STARVE_LIMIT
(4)
IODELAY_GRP
PAYLOAD_WIDTH
DEBUG_PORT
TCQ
tCK
DIFF_TERM_SYSCLK
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Description
This is the memory DQ bus width.
This is the memory DQS bus width.
This is the memory data burst length.
This is the number of bits required to index a
bank machine and is given by
ceil(log (nBANK_MACHS)).
2
This parameter is used by the controller to
calculate timing on the memory addr/cmd bus.
This parameter should not be changed.
This option reorders received requests to
optimize data throughput and latency.
This sets the number of times a read request
can lose arbitration before the request declares
itself high priority. The actual number of lost
arbitrations is STARVE_LIMIT × nBANK_MACHS.
This is an ASCII character string to define an
IDELAY group used in a memory design. This is
used by the Vivado tools to group all
instantiated IDELAYs into the same bank.
Unique names must be assigned when multiple
IP cores are implemented on the same FPGA.
This is the actual DQ bus used for user data.
This option enables debug signals/control.
This is the clock-to-Q delay for simulation
purposes.
This is the memory tCK clock period (ps).
"TRUE," "FALSE"
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Options
This parameter supports DQ widths
from 8 to a maximum of 72 in
increments of 8. The available
maximum DQ width is frequency
dependent on the selected memory
device.
DQ_WIDTH/8
LPDDR2: "8"
"1T"
"NORM": Allows the Memory
Controller to reorder read but not
write commands to the memory.
"RELAXED": Allows the Memory
Controller to reorder commands to
the memory for maximum
efficiency. Strong ordering is not
preserved at the native interface in
this mode.
"STRICT": Forces the Memory
Controller to execute commands in
the exact order received.
1, 2, 3, ... 10
Default: "IODELAY_MIG"
PAYLOAD_WIDTH = DATA_WIDTH
"ON"
"OFF"
(The value is in picoseconds.)
The value, in picoseconds, is based
on the selected frequency in the
MIG tool.
Differential termination for system
clock input pins.
623
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