Xilinx Zynq-7000 User Manual page 152

Memory interface solutions
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Table 1-60: Starting Scenarios for Write DQS (Cont'd)
Start DQS
f2z
Not
Case 3
Found
Found
Not
Case 4
Found
Found
Case 1
Found
Found
Not
Case 2
Found
Found
Not
Case 3
Found
Found
Not
Case 1
Found
Found
Not
Not
Case 2
Found
Found
Not
Not
Case 3
Found
Found
During the centering substage the write DQS is centered in the write DQ window based on
the edges found during the edge detection stage. At the end of this stage, write DQS should
be centered in the write DQ window. DQS to CK are not correct therefore write leveling is
performed at the end of this stage of calibration.
With every stage 3 tap decrease, the stage 2 taps are increased by 2 to maintain the DQS to
CK relationship established during write leveling. Similarly, with every stage 3 tap
increment, the stage 2 taps are decreased by 2. If stage 2 taps reach 0 or 63, stage 3 tap
increment/decrement is allowed to proceed up to the left and right limit values to avoid
violation. At the end of this stage of calibration, write leveling is redone to align DQS
t
DQSS
and CK using stage 2 taps.
Write Calibration
Write calibration is performed after both stages of read leveling because correct data
pattern sequence detection is necessary for this stage of calibration. Write calibration is
required to align DQS to the correct CK edge. During write leveling, DQS is aligned to the
nearest rising edge of CK. However, this might not be the edge that captures the write
command. Depending on the interface type (UDIMM, RDIMM, or component), the DQS
could either be one CK cycle earlier than, one CK cycle later than, or aligned to the CK edge
that captures the write command.
the initial phase relationship between DQS and CK for a UDIMM or RDIMM interface.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
z2f
f2o
o2f
Not
Not
Found
Found
Not
Not
Found
Found
Noise/Jitter Region
Not
Found
Found
Found
Found
Not
Found
Found
Fall Window 180
Found
Found
Found
Found
Not
Found
Found
Figure 1-67
www.xilinx.com
Center Equation
(fuzz2zero + lim2ocal_stg3_right_lim)/2
(lim2ocal_stg3_left_lim + zero2fuzz)/2
(fuzz2zero + zero2fuzz)/2
(zero2fuzz + fuzz2oneeighty)/2 – 90
(zero2fuzz + fuzz2oneeighty)/2 – 90
o
o
to 225
(zero2fuzz + fuzz2oneeighty)/2 – 90
(fuzz2oneeighty + oneeighty2fuzz)/2 – 180
(fuzz2oneeighty + lim2ocal_stg3_right_lim)/2 – 180
shows several different scenarios based on
o
o
o
o
o
152
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