Xilinx Zynq-7000 User Manual page 263

Calibration Times
For Initial ES (IES) with extended calibration, completing calibration in hardware should take
about 30 seconds.
For General ES (GES) and Production, hardware calibration time scales with interface data
width and data rate.
800 Mb/s and 1,600 Mb/s. Calibration times are faster at higher frequencies because the
required number of reads and writes to perform the phase adjustment can complete faster
than at a lower frequency. Calibration is completed on a per-byte basis. Therefore, larger
interface widths result in longer calibration times.
These are typical values. Calibration times can vary significantly depending on the board
Note:
signal integrity, the FPGA, and the frequency of operation.
MIG release 2014.2 includes updates to the read calibration algorithm resulting in
calibration time increase compared to the previous release. MIG release 2014.4 includes
updates to the write calibration algorithm using MMCM for better write DQS to write data
centering which resulted in increased calibration time.
Table 1-82: Calibration Time in Hardware
Calibration Time at 800 Mb/s (4:1) Calibration Time at 1,600 Mb/s (4:1)
MIG Release
2014.1 < 1 second
2014.2 < 1 second
2014.4 < 1 second
2015.1 ~1 second
Debugging Data Errors
General Checks
As with calibration error debug, the General Checks section of this answer record should be
reviewed. Strict adherence to proper board design is critical in working with high speed
memory interfaces. Violation of these general checks is often the root cause of data errors.
Replicating the Error Using the Traffic Generator
When data errors are seen during normal operation, the MIG 7 series Example Design
(Traffic Generator) should be used to replicate the error. The Traffic Generator can be
configured to send a wide range of data, address, and command patterns allowing
customers to test their target traffic pattern on a verified solution. The Traffic Generator
stores the write data and compares it to the read data. This allows comparison of expected
and actual data when errors occur. The following section details the critical step in Data
Error debug.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Table 1-82 lists the calibration times for 32-bit and 72-bit interfaces at
32-bit 72-bit
< 1 second
~1 second
~2 seconds
~2 seconds
www.xilinx.com
32-bit
< 1 second < 1 second
< 1 second Little over 1 second
< 1 second ~1 second
< 1 second ~1 second
72-bit
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