Xilinx Zynq-7000 User Manual page 473

• Write Data clock (DK_P/N) does not require an external termination, as On-Die
Termination is sufficient.
• Input Clock (CK_P/N) should be differentially terminated with an 80Ω resistor.
• Read Data clock (QK_P/N) does not require an external termination and should use DCI.
Set DCI termination to 40Ω for operation at and above 1,333 Mb/s, or 50Ω if operating
below 1,333 Mb/s.
Manual Pinout Changes
For manually manipulating the parameters described in
show how to allocate parameters for a given byte lane.
II data byte lane, indicating the bank, byte lane, and bit position for each signal.
Table 3-16: Example RLDRAM II Byte Lane #1
Byte
Bank Bit
Lane
9
8
7
6
B
A DK0_N
0 0
5
4
3
2
1
0
The byte lane parameters for
Table 3-17: Parameters for Example RLDRAM II Data Byte Lane #1
Parameter
DK_MAP
DQTS_MAP
PHY_0_BITLANES
DATA0_MAP
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Byte I/O
DDR
Group Type
VREF A_11 P
DQ8 A_10 N
DQ7 A_09 P
DQ6 A_08 N
DK0_P A_07 P
A_06 N
DQ5 A_05 P
DQ4 A_04 N
DQ3 A_03 P
DQ2 A_02 N
DQ1 A_01 P
DQ0 A_00 N
VRN N/A SE
Table 3-16
108'h008_007_006_005_004_003_002_001_000
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Table
Table 3-16
I/O Special
Number Designation
12 VREF
11
10
9
8 DQS-P
7 DQS-N
6
5
4
3
2
1
0
are shown in Table
Value
8'h00
12'h00A
12'h1FF
3-15, the following examples
shows a typical RLDRAM
BITLANES
0
1
1
1
0 0001
0
111
1
1
1 F
1
1
111
1
1
1 F
3-17.
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1
1FF
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