Xilinx Zynq-7000 User Manual page 73

Table 1-12: Example Settings for Address Space and PRBS Masks (Cont'd)
SADDR
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
Traffic Generator Signal Description
Traffic generator signals are described in
Table 1-13: Traffic Generator Signal Descriptions
Signal
clk_i
memc_init_done
manual_clear_error
memc_cmd_addr_o[31:0]
memc_cmd_en_o
memc_cmd_full_i
memc_cmd_instr[2:0]
memc_rd_data_i[DWIDTH – 1:0]
memc_rd_empty_i
memc_rd_en_o
memc_wr_data_o[DWIDTH –
1:0]
memc_wr_en_o
memc_wr_full_i
qdr_wr_cmd_o
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
EADDR PRBS_SADDR_MASK_POS
0xAFFF 0x00002000
0xBFFF 0x00002000
0xCFFF 0x00002000
0xDFFF 0x00002000
0xEFFF 0x00002000
0xFFFF 0x00002000
Direction Description
Input This signal is the clock input.
This is the input status signal from the Memory Controller to
Input
indicate that it is ready accept traffic.
Input Input signal to clear error flag.
Output Start address for current transaction.
This active-High signal is the write-enable signal for the Command
Output
FIFO.
This connects to inversion of app_rdy of Memory Controller. When
this input signal is asserted, TG continues to assert the
Input
memc_cmd_en_o, memc_cmd_addr_o value and memc_cmd_instr
until the memc_cmd_full_i is deasserted.
Command code for current instruction.
Output Command Write: 3'b000
Command Read: 3'b001
Input Read data value returning from memory.
This active-High signal is the empty flag for the Read Data FIFO in
Input
Memory Controller. It indicates there is no valid data in the FIFO.
Output This signal is only used in MCB-like interface.
Write data value to be loaded into Write Data FIFO in Memory
Output
Controller.
This active-High signal is the write enable for the Write Data FIFO.
Output
It indicates that the value on memc_wr_data is valid.
This active-High signal is the full flag for the Write Data FIFO from
Memory Controller. When this signal is High, TG holds the write
Input
data value and keeps assertion of memc_wr_en until the
memc_wr_full_i goes Low.
This signal is only used to send write commands to the QDR II+
Output
user interface.
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PRBS_EADDR_MASK_POS
0xFFFF0000
0xFFFF0000
0xFFFF0000
0xFFFF0000
0xFFFF0000
0xFFFF0000
Table 1-13.
73
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