Xilinx Zynq-7000 User Manual page 270

• Check the IDELAY values after calibration. Look for variations between IDELAY values.
IDELAY values should be very similar for DQs in the same DQS group.
• For debugging purposes only, vary the IDELAY taps after calibration for the bits that are
returning bad data.
Checking and Varying Read Timing
Debug signals are provided to verify read window margin on a per-byte basis and should be
used for debugging purposes only. Determining if sufficient margin is available for reliable
operation can be useful for debugging purposes if data errors are seen after calibration.
There is an automated window check flow that can be used to step through the entire
interface and provides the # of PHASER taps required to reach the left edge and right edge
of the data window. The window checking can also be manually verified by manually
incrementing and decrementing the PHASER taps to verify how much window margin is
available.
Table 1-85: Debug Signals Used for Checking and Varying Read/Write Timing
Signal Name
win_start
win_sel_pi_pon
vio_dbg_sel_pi_incdec
vio_dbg_pi_f_inc
vio_dbg_pi_f_dec
vio_win_byte_select_inc
vio_win_byte_select_dec
dbg_pi_counter_read_val
pi_win_left_ram_out
pi_win_right_ram_out
win_active
win_current_byte
win_byte_select
dbg_clear_error
vio_sel_mux_rdd[3:0]
Automated Window Check
The automated window checking is enabled by asserting win_start with a single pulse.
win_active should then assert until all byte groups have been measured.
win_sel_pi_pon must be set to 0x1 to enable Read window measurement. and
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Single pulse that starts the window check logic.
Controls window check logic on read path. Valid settings are:
• 0x1 = Enables Read Path
Enables manual incrementing and decrementing of the PHASER_IN taps.
Increments PHASER_IN fine taps when win_sel_pi_pon = 0x1.
Decrements PHASER_IN fine taps when win_sel_pi_pon = 0x1.
Increments the byte group being checked by the window margin check module.
Decrements the byte group being checked by the window margin check module.
Current PHASER_IN tap count corresponding to current byte being checked.
PHASER_IN tap count to reach the left edge of the read window for a given byte.
PHASER_IN tap count to reach the right edge of the read window for a given byte.
Flag to indicate the Window check logic is active and measuring window margins.
While active, the other VIOs should not be changed.
Feedback to indicate which byte is currently being monitored.
Selects which byte group to display the measured results for.
Clears error in Traffic Generator as a result of changing tap values.
Selects the byte for which the phaser increments or decrements are applied.
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