Xilinx Zynq-7000 User Manual page 199

Memory interface solutions

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The maximum electrical delay between any address and control signals and the

corresponding CK/CK# must be ≤ ±25 ps, with 8 ps being the optimal target.

CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The

skew allowed between CK/CK# and DQS/DQS# must be bounded between 0 and

1,600 ps. The recommended skew between CK/CK# and DQS/DQS# is 150 ps to

1,600 ps for components/UDIMMs and for RDIMMs it is 450 ps to 750 ps. For DIMM

modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the

memory components on the DIMM must be accounted for when designing to this

requirement.

CK/CK# must arrive after DQS/DQS# at each memory component to ensure calibration

can align DQS/DQS# to the correct CK/CK# clock cycle. Write Calibration failures are

seen if this specification is violated. See

(dbg_wrcal_err = 1), page 253

The specified DQ to DQS skew limit can be increased if the memory interface is not operated

at the maximum frequency.

The vertical axis is the bit rate in Mb/s. The first column is the FPGA maximum rate, check

the data sheet to determine this maximum rate. The second column is the actual speed the

memory system is operating at. The horizontal axis is the DDR3 SDRAM component speed

Table 1-67: DQ to DQS Skew Limit

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1

UG586 November 30, 2016

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Debugging DDR3/DDR2 Designs, page

indicates the relaxed skew limit (±) for these cases.

Memory Component Rating

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Debugging Write Calibration Failures

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