Xilinx Zynq-7000 User Manual page 663

Chapter 5: Multicontroller Design
X-Ref Target - Figure 5-24
Figure 5-24: Generate Window
8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources >
Libraries tab (Figure 5-25).
X-Ref Target - Figure 5-25
Figure 5-25: Vivado Project – RTL and Constraints Files
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 663
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UG586 November 30, 2016 www.xilinx.com