Xilinx Zynq-7000 User Manual page 369

When running the core in hardware, a few key signals should be inspected to determine the
status of the design. The dbg_phy_status bus described in
bits for various stages of calibration. Checking the dbg_phy_status bus gives initial
information that can aid in debugging an issue that might arise, determining which portion
of the design to look at, or looking for some common issues.
Table 2-16: Physical Layer Simple Status Bus Description
Debug Port Signal Name
dbg_phy_status[0] rst_wr_clk
io_fifo_rden_cal_done &
dbg_phy_status[1] po_ck_addr_cmd_delay_
done
dbg_phy_status[2] init_done
dbg_phy_status[3] cal_stage1_start
dbg_phy_status[4] edge_adv_cal_done
dbg_phy_status[5] cal_stage2_start
cal_stage2_start &
dbg_phy_status[6]
cal_done
dbg_phy_status[7] Cal_done
Notes:
1. N/A indicates that as long as previous stages have completed, this stage is also completed.
The read calibration results are provided as part of the Debug port as various output
signals. These signals can be used to capture and evaluate the read calibration results.
Read calibration uses the IODELAY to align the capture clock in the data valid window for
captured data. The algorithm shifts the IODELAY values and looks for edges of the data valid
window on a per-byte basis as part of the calibration procedure.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
Description
FPGA logic reset based on
PLL lock and system input
reset
I/O FIFO initialization to
ensure the I/O FIFOs are
in an almost full condition
and the phaser out delay
to provide the 90° phase
shift to address/control
signals are done
SRAM
QDR II+
initialization sequence is
complete
Stage 1 read calibration
start signal
Stage 1 calibration is
complete and edge_adv
calibration is complete
Latency calibration start
signal after pi_edge_adv
calibration is completed.
Latency calibration start
signal
Calibration complete
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Table 2-16 consists of status
If Issues Arise
If this signal stays asserted,
check your clock source and
system reset input
Check if the PHY control ready
signal is asserted
(1)
N/A
N/A
Stage 1 calibration did not
happen right. Make sure valid
read data is seen during stage1
calibration.
If this signal does not go High,
then stage 1 has not completed.
Make sure the expected data is
being returned from the
memory.
N/A
N/A
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