Customizing The Core - Xilinx Zynq-7000 User Manual

X-Ref Target - Figure 3-60

Customizing the Core

The RLDRAM II/RLDRAM 3 memory interface solution is customizable to support several
configurations. The specific configuration is defined by Verilog parameters in the top-level
of the core. As per the OOC flow, none of the parameter values are passed down to the user
design RTL file from the example design top RTL file. So, any design related parameter
change is not reflected in the user design logic. The MIG tool should be used to regenerate
a design when parameters need to be changed. The parameters are summarized in
Table 3-14.
Table 3-14: RLDRAM II Memory Interface Solution Configurable Parameters
Parameter
CLK_PERIOD
ADDR_WIDTH
RLD_ADDR_WIDTH
BANK_WIDTH
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-60: RLDRAM II Write Calibration Waveforms
Description
Memory clock period (ps).
Memory address bus width.
Physical Memory address bus width when using Address
Multiplexing mode.
Memory bank address bus width.
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RLDRAM II: 3
RLDRAM 3: 4
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