Xilinx Zynq-7000 User Manual page 61

user_design/rtl/clocking
This directory contains the user design
Table 1-5: Files in user_design/rtl/clocking Directory
(1)
Name
clk_ibuf.v
iodelay_ctrl.v
infrastructure.v
Notes:
1. All file names are prefixed with the MIG core version number. For example, for the MIG 4.1 release module name
of clk_ibuf in generated output is now mig_7series_v4_1_clk_ibuf.
user_design/rtl/controller
This directory contains the Memory Controller that is instantiated in the example design
(Table 1-6).
Table 1-6: Files in user_design/rtl/controller Directory
(1)
Name
arb_mux.v
arb_row_col.v
arb_select.v
bank_cntrl.v
bank_common.v
bank_compare.v
bank_mach.v
bank_queue.v
bank_state.v
col_mach.v
mc.v
mem_intfc.v
rank_cntrl.v
rank_common.v
rank_mach.v
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
(Table 1-5).
Description
This module instantiates the input clock buffer.
This module instantiates IDELAYCNTRL primitives needed for
IDELAY use.
This module helps in clock generation and distribution, and reset
synchronization.
Description
This is the top-level module of arbitration logic.
This block receives requests to send row and column commands from the
bank machines and selects one request, if any, for each state.
This module selects a row and column command from the request
information provided by the bank machines.
This structural block instantiates the three subblocks that comprise the
bank machine.
This module computes various items that cross all of the bank machines.
This module stores the request for a bank machine.
This is the top-level bank machine block.
This is the bank machine queue controller.
This is the primary bank state machine.
This module manages the DQ bus.
This is the top-level module of the Memory Controller.
This top-level memory interface block instantiates the controller and the
PHY.
This module manages various rank-level timing parameters.
This module contains logic common to all rank machines. It contains a
clock prescaler and arbiters for refresh and periodic read.
This is the top-level rank machine structural block.
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