Xilinx Zynq-7000 User Manual page 277

4. Click Next to proceed to the Project Type page
RTL Project because MIG deliverables are RTL files.
X-Ref Target - Figure 2-4
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
(Figure
Figure 2-4: Project Type
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2-4). Select the Project Type as
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