Using Mig In The Vivado Design Suite - Xilinx Zynq-7000 User Manual

Using MIG in the Vivado Design Suite

This section provides the steps to generate the Memory Interface Generator (MIG) IP core
using the Vivado Design Suite and run implementation.
1. Start the Vivado Design Suite (see
X-Ref Target - Figure 5-1
2. To create a new project, click the Create New Project option shown in
open the page as shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Figure 5-1).
Figure 5-1: Vivado Design Suite
Figure 5-2.
www.xilinx.com
Chapter 5: Multicontroller Design
Figure 5-1
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