Xilinx Zynq-7000 User Manual page 601

X-Ref Target - Figure 4-50
From
PHY
Control
Block
Mem_Ref_Clk
PHY_Cmd_AlmostFull
PHY_Cmd_Full
PHY_CA[19:0],PHY_CS_N
PHY_Clk
PHY_Cmd_WrEn
From
PHY
Control
Block
From
PHY
Control
Block
From
PHY
Control
Block
The timing diagram of the address/command path from the output of the OUT_FIFO to the
FPGA pins is shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Enable_Calib[1:0] OClk1x
Burst_Pending OClk1x90
RankSel[1:0] OClkDiv
Phaser
DQS[1:0]
Out B
PhaseRef
CTS[1:0]
DTS[1:0]
FreqRef
RdEnable
Out_FIFO_B
D Q
OF_RE_B
In_FIFO_A
Q D
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0] IClk1x
Phaser
IClkDiv
In B
PhaseRef RClk
FreqRef WriteEnable
Enable_Calib[1:0] OClk1x
Burst_Pending OClk1x90
RankSel[1:0] OClkDiv
Phaser
DQS[1:0]
Out A
PhaseRef
CTS[1:0]
DTS[1:0]
FreqRef
RdEnable
Out_FIFO_A
D Q
OF_RE_A
In_FIFO_A
Q D
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0] IClk1x
Phaser
IClkDiv
In A
PhaseRef RClk
FreqRef WriteEnable
Figure 4-50: Address/Command Path Block Diagram
Figure 4-51.
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Cmd Byte Group B
Note: CK is implemented as an ODDR clocked by
DDR_Clkdelayed
DDR_Clkdelayed_B
RAS_N, CAS_N, WE_N, BA[2:0], A[15:12]
DDR_Clk_B
DDR_DivClk_B
BUFIO
Cmd Byte Group A
A[11:0]
DDR_Clk_A
DDR_DivClk_A
0
OBUF
ODDR Byte
1
Group B
OBUF
OSERDES
Byte Group
DDR_DivR_Clk
OBUF
OSERDES
Byte Group
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