Xilinx Zynq-7000 User Manual page 240

Table 1-74: DDR2/DDR3 Debug Signals (Cont'd)
Signal Name
dbg_mux_rd_valid_r
dbg_cpt_first_edge_cnt_by_dqs
dbg_cpt_second_edge_cnt_by_dqs
dbg_cpt_tap_cnt_by_dqs
dbg_dq_idelay_tap_cnt_by_dqs
dbg_dbg_calib_rd_data_offset_1
dbg_dbg_calib_rd_data_offset_2
dbg_data_offset
dbg_data_offset_1
dbg_data_offset_2
dbg_cpt_first_edge_cnt
dbg_cpt_second_edge_cnt
dbg_cpt_tap_cnt
dbg_dq_idelay_tap_cnt
dbg_prbs_rdlvl
dbg_ocal_lim_done
dbg_ocal_stg3_lim_left
dbg_ocal_stg3_lim_right
dbg_ocal_center_calib_start
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Asserts when the valid pattern is detected on dbg_mux_rd_rise0_r,
dbg_mux_rd_fall0_r, dbg_mux_rd_rise1_r, dbg_mux_rd_fall1_r,
dbg_mux_rd_rise2_r, dbg_mux_rd_fall2_r, dbg_mux_rd_rise3_r, and
dbg_mux_rd_fall3_r.
Signifies PHASER_IN fine tap count when the first edge in MPR and
Read Leveling Stage 1 is found. Byte capture based on VIO dbg_dqs
setting.
Signifies PHASER_IN fine tap count when then second edge in MPR
and Read Leveling Stage 1 is found. Byte capture based on VIO
dbg_dqs setting.
Signifies the center tap moved to based on when the first and second
edges were found. Byte capture based on VIO dbg_dqs setting.
IDELAY tap value for MPR and Read Leveling Stage 1. This should be
within 2 to 3 taps across all DQS byte groups. Byte capture based on
VIO dbg_dqs setting.
Read data offset found during calibration.
Read data offset found during calibration.
Data Offset used during normal operation. Value changes during
writes, reads, and idle. During writes, it is CWL + 2+slot#. During
non-data commands, it is 0. During reads, it should match what was
found during DQSFOUND calibration (rd_data_offset_ranks).
Data Offset used during normal operation. Value changes during
writes, reads, and idle. During writes, it is CWL + 2+slot#. During
non-data commands, it is 0. During reads, it should match what was
found during DQSFOUND calibration (rd_data_offset_ranks).
Data Offset used during normal operation. Value changes during
writes, reads, and idle. During writes, it is CWL + 2+slot#. During
non-data commands, it is 0. During reads, it should match what was
found during DQSFOUND calibration (rd_data_offset_ranks).
Signifies PHASER_IN fine tap count when the first edge in MPR and
Read Leveling Stage 1 is found.
Signifies PHASER_IN fine tap count when then second edge in MPR
and Read Leveling Stage 1 is found.
Center PHASER_IN fine tap value in MPR or Read Leveling Stage 1 is
found.
IDELAY tap value for MPR and Read Leveling Stage 1. This should be
within 2 to 3 taps across all DQS byte groups. Byte capture based on
VIO dbg_dqs setting.
Debug signals of PRBS Read Level Stage.
Indicates that stage 3 lower and upper limits have been determined.
Stage 3 lower limit.
Stage 3 upper limit.
OCLKDELAY center calibration start indicator.
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