Xilinx Zynq-7000 User Manual page 334

Calibration of Read Clock and Data
The PHASER_IN/PHASER_OUT clocks within each byte group are used to clock all ISERDES
used to capture read data (Q) associated with the corresponding byte group. ICLKDIV is also
the write clock for the read data IN_FIFOs. One PHASER_IN block is associated with a group
of 12 I/Os. Each I/O bank in the 7 series FPGA has four PHASER_IN blocks, and hence four
read data bytes can be placed in a bank.
Implementation Details
This stage of read leveling is performed one byte at a time where the read clock is center
aligned to the corresponding read data in that byte group. At the start of this stage, a write
command is issued to a specified QDR II+ SRAM address location with a specific data
pattern. This write command is followed by back-to-back read commands to continuously
read data back from the same address location that was written to.
The calibration logic reads data out of the IN_FIFO and records it for comparison. The
calibration logic checks for the sequence of the data pattern read to determine the
alignment of the clock with respect to the data. No assumption is made about the initial
relationship between the capture clock and the data window at tap 0 of the fine delay line.
The algorithm tries to align the rise and fall clocks to the left edge of their corresponding
data window, by delaying the read data through the IDELAY element.
Next, the clocks are then delayed using the PHASER taps and centered within the
corresponding data window. The PHASER_TAP resolution is based on the FREQ_REF_CLK
period and the per-tap resolution is equal to (FREQ_REFCLK_PERIOD/2)/64 ps. For memory
interface frequencies ≥ 400 MHz, using the maximum of 64 PHASER taps can provide a
delay of 1 data period or 1/2 the clock period. This enables the calibration logic to
accurately center the clock within the data window.
For frequencies < 400 MHz, because FREQ_REF_CLK has twice the frequency of the
MEM_REF_CLK, the maximum delay that can be derived from the PHASER is 1/2 the data
period or 1/4 the clock period. Hence for frequencies < 400 MHz, just using the PHASER
delay taps might not be sufficient to accurately center the clock in the data window. So for
these frequency ranges, a combination of both data delay using IDELAY taps and PHASER
taps is used. The calibration logic determines the best possible delays, based on the initial
clock-data alignment.
The next step is to increment the fine phase shift delay line of the PHASER_IN and
PHASER_OUT blocks one tap at a time until a data mismatch is detected. The data read out
of IN_FIFO after the required settling time is then compared with the recorded data at the
previous tap value. This is repeated until a data mismatch is found, indicating the detection
of a valid data window edge.
Complex pattern read calibration stage is added as the last stage of calibration to improve
margin.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
www.xilinx.com
334
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