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Xilinx 7 Series User Manual

Fpgas configurable logic block
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7 Series FPGAs
Configurable Logic Block
User Guide
UG474 (v1.8) September 27, 2016

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  • Page 1 7 Series FPGAs Configurable Logic Block User Guide UG474 (v1.8) September 27, 2016...

  • Page 2: Revision History

    Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail- safe or for use in any application requiring fail-safe performance;...
  • Page 3 Updated Table 1-2 for new Artix 7A15T device. 09/27/2016 Added Spartan®-7 device family (updated Preface and added Table 1-1). Added Artix®-7 7A12T and 7A25T devices to Table 1-2. UG474 (v1.8) September 27, 2016 www.xilinx.com 7 Series FPGAs CLB User Guide...
  • Page 4 7 Series FPGAs CLB User Guide www.xilinx.com UG474 (v1.8) September 27, 2016...

  • Page 5: Table Of Contents

    CLB Slice Carry-Chain Timing Model and Parameters ..... . . 61 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback...
  • Page 6 ............72 Devices Using Stacked Silicon Interconnect (SSI) Technology ....73 www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 7: Preface: About This Guide

    Preface About This Guide Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio.

  • Page 8: Additional Support Resources

    Timing, contains timing models and defines CLB timing specifications from the respective 7 series FPGA data sheet. • Chapter 6, Advanced Topics, discusses advanced features of the 7 series CLB. Additional Support Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support.html#documentation...

  • Page 9: Chapter 1: Overview

    Figure 1-1: Arrangement of Slices within the CLB The LUTs in 7 series FPGAs can be configured as either a 6-input LUT with one output, or as two 5-input LUTs with separate outputs but common addresses or logic inputs. Each 5-input LUT output can optionally be registered in a flip-flop.

  • Page 10: Series Clb Features

    Expert designers can also instantiate them. 7 Series CLB Features The 7 series CLB is identical to that in the Virtex®-6 FPGA family. The CLB is very similar to that of the Spartan®-6 FPGA family with these differences: •...
  • Page 11 Notes: 1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs. 2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.

  • Page 12: Recommended Design Flow

    Notes: 1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs. 2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.

  • Page 13: Pinout Planning

    Carry logic cascades vertically up a column, so wide arithmetic buses might drive a vertical orientation to other logic, including I/O. While most 7 series devices are available in flip-chip packages, taking full advantage of the distributed I/O in the ASMBL architecture, the smaller devices are available in wire-bond packages at a lower cost.
  • Page 14 Chapter 1: Overview www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 15: Chapter 2: Functional Details

    Dedicated gates and cascading to implement efficient arithmetic functions CLB Arrangement The CLBs are arranged in columns in the 7 series FPGAs. The 7 series is the fourth generation to be based on the unique columnar approach provided by the ASMBL™...
  • Page 16 SSI Technology The 7 series FPGAs extend integration even higher by using the unique stacked silicon interconnect (SSI) technology. SSI technology enables multiple super logic regions (SLRs) to be combined on a passive interposer layer, to create a single FPGA with more than ten thousand inter-SLR connections.
  • Page 17 CLB Arrangement The Xilinx tools designate slices with these definitions: • An “X” followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB column);...

  • Page 18: Slice Description

    SLICEL is shown in Figure 2-4. Each CLB can contain two SLICEL or a SLICEL and a SLICEM. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 19 FF/LAT INIT1 INIT0 SRHI SRLO MC31 SRHI SRLO INIT1 INIT0 AMUX A6:1 A6:A1 W6:W1 FF/LAT INIT1 INIT0 SRHI SRLO MC31 UG474_c2_02_110510 Figure 2-3: Diagram of SLICEM 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 20 BMUX B6:1 A6:A1 FF/LAT INIT1 INIT0 SRHI SRLO SRHI SRLO INIT1 INIT0 AMUX A6:1 A6:A1 FF/LAT INIT1 INIT0 SRHI SRLO UG474_c2_03_101210 Figure 2-4: Diagram of SLICEL www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 21: Look-Up Table (Lut)

    Look-Up Table (LUT) Look-Up Table (LUT) The function generators in 7 series FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement: •...
  • Page 22 These initialization options are available for storage elements: • SRLOW: Synchronous or asynchronous Reset when CLB SR signal is asserted • SRHIGH: Synchronous or asynchronous Set when CLB SR signal is asserted www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 23: Distributed Ram (Available In Slicem Only)

    The initial state after configuration or global initial state is defined by separate INIT0 and INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. 7 series devices can set INIT0 and INIT1 independent of SRHIGH and SRLOW.
  • Page 24 Table 2-3 shows the number of LUTs (four per slice) occupied by each distributed RAM configuration. See UG953, Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for details of available distributed RAM primitives. Table 2-3: Distributed RAM Configuration...
  • Page 25 When using x2 configurations (as in 32 X 2 Quad Port in Figure 2-6), A6 and WA6 are driven High by the software to keep O5 and O6 independent. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 26 DOC[1] DPRAM32 DOB[0] B[5:1] ADDRB[4:0] A[6:1] WA[6:1] DOB[1] DPRAM32 DOA[0] A[5:1] ADDRA[4:0] A[6:1] WA[6:1] DOA[1] UG474_c2_06_070914 Figure 2-6: 32 X 2 Quad Port Distributed RAM (RAM32M) www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 27 O[4] DATA[4] B[5:1] A[6:1] WA[6:1] O[3] DPRAM32 DATA[5] O[6] DATA[6] A[5:1] A[6:1] WA[6:1] O[5] UG474_c2_06_070914 Figure 2-7: 32 X 6 Simple Dual Port Distributed RAM (RAM32M) 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 28 A[6:1] Output WA[6:1] (CLK) (Optional) WCLK (WE/CE) DPRAM64 Registered (C[6:1]) DPRA[5:0] A[6:1] Output WA[6:1] (Optional) UG474_c2_08_101210 Figure 2-9: 64 X 1 Dual Port Distributed RAM (RAM64X1D) www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 29 (B[6:1]) Registered ADDRB A[6:1] Output WA[6:1] (Optional) DPRAM64 (A[6:1]) Registered ADDRA A[6:1] Output WA[6:1] (Optional) UG474_c2_09_070914 Figure 2-10: 64 X 1 Quad Port Distributed RAM (RAM64M) 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 30 RAM128X1S primitives can occupy a SLICEM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 31 A[6:0] A[6:1] WA[7:1] (CLK) WCLK (WE/CE) Output Registered SPRAM64 F7BMUX Output (Optional) [5:0] A[6:1] WA[7:1] UG474_c2_11_101210 Figure 2-12: 128 X 1 Single Port Distributed RAM (RAM128X1S) 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 32 Output (Optional) A[6:1] WA[7:1] DPRAM64 DPRA[6:0] A[6:1] WA[7:1] Registered DPRAM64 F7AMUX Output (Optional) A[6:1] WA[7:1] UG474_c2_12_101210 Figure 2-13: 128 X 1 Dual Port Distributed RAM (RAM128X1D) www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 33 Distributed RAM configurations greater than the provided examples require more than one SLICEM. There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback...

  • Page 34: Shift Registers (Available In Slicem Only)

    SLICEM. There are no direct connections between slices to form longer shift registers, nor is the MC31 output at LUT B/C/D available. The resulting programmable delays can be used to balance the timing of data pipelines. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 35 SHIFTIN (MC31 of Previous LUT) SRL32 (AI) SHIFTIN (D) MC31 SHIFTOUT (Q31) (A[6:2]) A[4:0] A[6:2] (CLK) Output (Q) (WE/CE) (AQ) Registered Output (Optional) UG474_c2_14_110510 Figure 2-15: 32-Bit Shift Register Configuration 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 36 16-bit shift registers. The example shown can be implemented in a single LUT. For more information on the SRLC32E and SRL16E primitives, see UG953, Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide. X-Ref Target - Figure 2-17...
  • Page 37 (WE/CE) (BMUX) Output (Q) (BQ) Registered F8MUX Output (Optional) SRL32 A[6:2] MC31 AX (A5) SRL32 Not Used F7AMUX A[6:2] UG474_c2_18_101210 Figure 2-19: 96-Bit Shift Register Configuration 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 38 • The input (D) is loaded into the first bit of the shift register • Each bit is also shifted to the next highest bit position www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 39: Multiplexers

    In a cascadable configuration, the Q31 output always contains the last bit value • The Q31 output changes synchronously after each shift operation Multiplexers Function generators and associated multiplexers in 7 series FPGAs can implement these functions: • 4:1 multiplexers using one LUT •...
  • Page 40 4:1 MUX Output (A[6:1]) (AQ) Registered SEL A [1:0], DATA A [3:0] A[6:1] Output Input (CLK) (Optional) UG474_c2_20_101210 Figure 2-21: Four 4:1 Multiplexers in a Slice www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 41 Output (2) (AQ) Registered Output (A[6:1]) SEL A [1:0], DATA A [3:0] A[6:1] Input (2) (Optional) (AX) SELF7(2) UG474_c2_21_101210 Figure 2-22: Two 8:1 Multiplexers in a Slice 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 42 It is possible to create multiplexers wider than 16:1 across more than one SLICEM. However, there are no direct connections between slices to form these wide multiplexers. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 43: Carry Logic

    Carry Logic Carry Logic In addition to function generators, dedicated fast lookahead carry logic is provided to perform fast arithmetic addition and subtraction in a slice. A 7 series FPGA CLB has two separate carry chains, as shown in Figure 1-1.
  • Page 44 (SLRs) in devices using stacked silicon interconnect (SSI) technology. See Devices Using Stacked Silicon Interconnect (SSI) Technology in Chapter www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 45: Chapter 3: Design Entry

    7 Series FPGAs Migration Methodology Guide). Refer to www.xilinx.com for good HDL coding techniques for FPGAs, such as in UG687, XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices. • Pipelining • The designer should use sequential design techniques and pipelining to take advantage of abundant flip-flops for performance.

  • Page 46: Using The Clb Resources

    Xilinx recommends using generic HDL code and allowing the tools to infer the usage of CLB resources. Using IP solutions designed for 7 series FPGAs can help make full use of the CLB resources. Although any feature in the CLB can be instantiated directly, including the LUTs, carry logic, and sequential elements, instantiation should be reserved primarily for specifying when resources outside the CLB should be used, such as the DSP slice.
  • Page 47 CO[3] is connected through COUT to the CI input of another CARRY4 primitive, and dedicated routing connects the carry chain up a column of slices. The carry outputs also optionally connect to the slice AMUX/BMUX/CMUX/DMUX outputs. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 48 The input and output data are one bit wide (with the exception of the quad-port RAM). Figure 3-3 shows generic single-port, dual-port, and quad-port distributed RAM primitives. The A, ADDR, and DPRA signals are address buses. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 49 Data In – D, DID[#:0] The data input D (for single-port and dual-port) and DID[#:0] (for quad-port) provide the new data value to be written into the RAM. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 50 (bit 31). Data Out – Q The data output Q provides the data value (1 bit) selected by the address inputs. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 51 The FDRE primitive is shown in Figure 3-5 for an example. For more information on the flip-flop and latch primitives, see UG953, Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide. X-Ref Target - Figure 3-5 FDRE...
  • Page 52 This signal is available in the FDPE component. The FDPE flip-flop is also preset by default on power-up. Note: Using both asynchronous clear and preset on the same flip-flop requires additional resources and timing paths. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 53: Chapter 4: Applications

    RAM for larger arrays. It is recommended to infer memory where possible to provide the greatest flexibility. Distributed RAM can also be targeted by instantiation or through the use of Xilinx LogiCORE™ IP. In general, distributed RAM should be used for all memories that consist of 64 bits or less, unless there is a shortage of SLICEM or logic resources for the target device.
  • Page 54 X-Ref Target - Figure 4-2 SRLC32E SRLC32E SRLC32E SRLC32E (72-bit SRL) (72-bit SRL) 00111 A[4:0] 00110 A[4:0] SRLC32E SRLC32E UG474_c4_02_101210 Figure 4-2: Example Static-Length Shift Register www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 55: Carry Logic Applications

    CLB slices and carry logic provide an efficient alternative. Using Carry Logic Carry logic can be inferred or instantiated. Using macros designed for the 7 series FPGA can provide the most flexibility and efficiency, especially for more complex functions.
  • Page 56 Chapter 4: Applications www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 57 Xilinx® Timing Analyzer and the section on switching characteristics in the respective 7 series FPGAs data sheet. All pin names, parameter names, and paths are consistent with the Timing Analyzer reports. Most of the CLB timing parameters found in the data sheet section on switching characteristics are described in this chapter.

  • Page 58: Clb General Slice Timing Model And Parameters

    Chapter 5: Timing CLB General Slice Timing Model and Parameters A simplified 7 series FPGA slice is shown in Figure 5-1. Only the elements relevant to the timing paths described in this section are shown. X-Ref Target - Figure 5-1...
  • Page 59 1. This parameter includes a LUT configured as two five-input functions. 2. T = Setup Time (before clock edge), and T = Hold Time (after clock edge). XXCK CKXX 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 60: Clb Slice Multiplexer Timing Model And Parameters

    Chapter 5: Timing General Timing Characteristics Figure 5-2 illustrates the general timing characteristics of a 7 series FPGA slice. X-Ref Target - Figure 5-2 CECK DICK AX/BX/CX/DX (DATA) SRCK SR (RESET) AQ/BQ/CQ/DQ (OUT) UG474_c5_02_102310 Figure 5-2: General Slice Timing Characteristics •...

  • Page 61: Clb Slice Carry-Chain Timing Model And Parameters

    CLB Slice Carry-Chain Timing Model and Parameters Figure 2-24, page 43 illustrates a carry chain in a 7 series FPGA slice. Slice Carry-Chain Timing Parameters Table 5-3 shows the slice carry-chain timing parameters for a majority of the paths in Figure 2-24.
  • Page 62 1, data from the CIN input becomes valid-High at CINCK the Data input of the slice register. This is reflected on any of the AQ/BQ/CQ/DQ pins at time T after clock event 1. www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 63: Clb Slice Distributed Ram Timing Model And Parameters (Available In Slicem Only)

    (Available in SLICEM Only) Figure 5-4 illustrates the details of distributed RAM implemented in a 7 series FPGA slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.
  • Page 64 1. T = Setup Time (before clock edge), and T = Hold Time (after clock edge). 2. Parameter includes AX/BX/CX/DX configured as a data input (DI2). www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 65 CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only) Distributed RAM Timing Characteristics The timing characteristics of a distributed RAM implemented in a 7 series FPGA slice (LUT configured as RAM) are shown in Figure 5-5. X-Ref Target - Figure 5-5...

  • Page 66: Clb Slice Srl Shift Register Timing Model And Parameters (Available In Slicem Only)

    (Available in SLICEM Only) Figure 5-6 illustrates shift register implementation in a 7 series FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.
  • Page 67 = Setup Time (before clock edge), and T = Hold Time (after clock edge). 3. Parameter includes AX/BX/CX/DX configured as a data input (DI2) or two bits with a common shift. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback...
  • Page 68 Chapter 5: Timing Slice SRL Timing Characteristics Figure 5-7 illustrates the timing characteristics of a shift register implemented in a 7 series FPGA slice (a LUT configured as an SRL). X-Ref Target - Figure 5-7 Write Enable (WE) Shift_In (DI)
  • Page 69 (logical 0 in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T after clock event 1. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...
  • Page 70 Chapter 5: Timing www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 71: Chapter 6: Advanced Topics

    UG474_c6_02_110310 Figure 6-2: Implementation of OR2L (Q = D or SRI) The device model shows these functions as AND2L and OR2L configurations of the storage element. 7 Series FPGAs CLB User Guide www.xilinx.com Send Feedback UG474 (v1.8) September 27, 2016...

  • Page 72: Interconnect Resources

    The 7 series CLBs are arranged in a regular array inside the FPGA. Each connects to a switch matrix for access to the general-routing resources, which run vertically and horizontally between the CLB rows and columns.

  • Page 73: Devices Using Stacked Silicon Interconnect (Ssi) Technology

    Devices Using Stacked Silicon Interconnect (SSI) Technology As noted in the DS180, 7 Series FPGAs Overview, some of the Virtex-7 devices use stacked silicon interconnect (SSI) technology. These devices provide a unique additional type of interconnect resource called a super long line or SLL. These special routing resources can be treated like other interconnect resources as they are abundant (more than 10,000) and fast (about 1 ns).
  • Page 74 DS180, 7 Series FPGAs Overview • Stacked Silicon Interconnect Technology page www.xilinx.com/products/silicon-devices/3dic.html • WP380, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency www.xilinx.com 7 Series FPGAs CLB User Guide Send Feedback UG474 (v1.8) September 27, 2016...

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