Xilinx Zynq-7000 User Manual page 64

Verify Pin Changes and Update Design
This feature verifies the input XDC for bank selections, byte selections, and pin allocation. It
also generates errors and warnings in a separate dialog box when you click Validate on the
page. This feature is useful to verify the XDC for any pinout changes made after the design
is generated from the MIG tool. You must load the MIG tool generated .prj file, the
original .prj file without any modifications, and the XDC that needs to be verified. In the
Vivado Design Suite, the recustomization option should be selected to reload the project.
The design is allowed to generate only when the MIG DRC is met. Ignore warnings about
validating the pinout, which is the intent. Just validating the XDC is not sufficient; it is
mandatory to proceed with design generation to get the XDC with updated clock and
phaser related constraints and RTL top-level module for various updated Map parameters.
The Update Design feature is required in the following scenarios:
• A pinout is generated using an older version of the MIG tool and the design is to be
revised to the current version of MIG. In MIG, the pinout allocation algorithms have
been changed for certain MIG designs.
• A pinout is generated independent of the MIG tool or is modified after the design is
generated. When a design is generated from the MIG tool, the XDC and HDL code are
generated with the correct constraints.
Here are the rules verified from the input XDC:
• If a pin is allocated to more than one signal, the tool reports an error. Further
verification is not done if the XDC does not adhere to the uniqueness property.
• Verified common rules:
The interface can span across a maximum of three consecutive banks.
°
Interface banks should reside in the same column of the FPGA.
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Interface banks should be either High Performance (HP) or High Range (HR). HP
°
banks are used for the high frequencies.
The chosen interface banks should have the same SLR region if the chosen device is
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of stacked silicon interconnect technology.
V I/Os should be used as GPIOs when an internal V
° REF
inout and input ports in a bank.
The I/O standard of each signal is verified as per the configuration chosen.
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The VCCAUX I/O of each signal is verified and provides a warning message if the
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provided VCCAUX I/O is not valid.
• Verified data pin rules:
Pins related to one strobe set should reside in the same byte group.
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The strobe pair (DQS) should be allocated to the DQS I/O pair.
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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is used or if there are no
REF
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