Xilinx Zynq-7000 User Manual page 374

Table 2-18: DEBUG_PORT Signal Descriptions (Cont'd)
Signal
dbg_error_adj_latency
dbg_align_rd0 [DATA_WIDTH – 1:0]
dbg_align_rd1 [DATA_WIDTH – 1:0]
dbg_align_fd0 [DATA_WIDTH – 1:0]
dbg_align_fd1 [DATA_WIDTH – 1:0]
dbg_cmplx_rd_loop
dbg_cmplx_rd_lane[2:0]
dbg_K_left_shift_right
dbg_K_right_shift_left
dbg_cmplx_wr_loop
Write Init Debug Signals
Table 2-19 indicates the mapping between the write init debug signals on the
dbg_wr_init bus and debug signals in the PHY. All signals are found within the
qdr_phy_write_init_sm module and are all valid in the clk domain.
Table 2-19: Write Init Debug Signal Map
Bits PHY Signal Name
dbg_wr_init[14:0] phy_init_r
dbg_wr_init[18:15] phase_valid
dbg_wr_init[22:19] lanes_solid_r
dbg_wr_init[23] po_delay_done
dbg_wr_init[24] rdlvl_stg1_done
dbg_wr_init[25] rdlvl_stg1_start
dbg_wr_init[26] edge_adv_cal_start
dbg_wr_init[27] edge_adv_cal_done
dbg_wr_init[28] cal_stage2_start
dbg_wr_init[29] read_cal_done
dbg_wr_init[30] rst_stg1_r
dbg_wr_init[31] rst_stg2_r
dbg_wr_init[32] suppress_stg1
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
Direction Description
This signal indicates that the target PHY_LATENCY could
Output
not be achieved
Output This bus shows the captured output of the first rising data
This bus shows the captured output of the second rising
Output
data
This bus shows the captured output of the first falling
Output
data
This bus shows the captured output of the second falling
Output
data
Input When High, complex read level continues forever.
Selects the lane to hang on when dbg_cmplx_rd_loop ==
Input
'b1.
Input Shifts the location of the left edge sent to the POC right.
Input Shifts the location of the right edge sent to the POC left.
Input When High, complex write pattern is written indefinitely.
Description
One hot state machine.
Per byte lane comparison results.
Comparison success post threshold per lane.
Phaser out adjustment complete.
Read level cycle complete.
Start read level calibration.
Start cycle (edge) alignment.
Edge alignment complete.
Start latency calibration.
Latency calibration complete.
Reset read level block.
Reset edge and latency calibration logic.
All bytes successfully read leveled. Suppress further
read levels.
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