Xilinx Zynq-7000 User Manual page 505

Table 3-28: DEBUG_PORT Signal Descriptions (Cont'd)
Signal
dbg_wrcal_done[2:0]
dbg_wrcal_po_first_edge[5:0]
dbg_wrcal_po_second_edge[5:0]
dbg_wrcal_po_final[5:0]
Write Init Debug Signals
Table 3-29 indicates the mapping between the write init debug signals on the
dbg_wr_init bus and debug signals in the PHY. All signals are found within the
rld_phy_write_init_sm module and are all valid in the clk domain.
Table 3-29: Write Init Debug Signal Map
Bits
dbg_phy_init_sm[3:0]
dbg_phy_init_sm[6:4]
dbg_phy_init_sm[7]
dbg_phy_init_sm[8]
dbg_phy_init_sm[9]
dbg_phy_init_sm[10]
dbg_phy_init_sm[22:11]
dbg_phy_init_sm[26:23]
dbg_phy_init_sm[31:27]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
PHY Signal Name Description
phy_init_cs Current state of the initialization state machine
start_cal Flags to determine stages of calibration
init_complete Memory initialization is complete
refr_req Refresh request
refr_done Refresh complete
stage2_done Stage 2 calibration is complete
refr_cnt Refresh counter
phy_init_ps Previous state of the initialization state machine
Reserved Reserved
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Direction Description
Indicates stage of write calibration
Output
completed.
First edge of write calibration window
found for the selected byte lane (using
dbg_byte_sel). To select a given stage of
Output calibration, use dbg_wrcal_sel_stg, 2'b01
is for byte lanes with a DK clock, and
2'b10 is for byte lanes without a DK
clock.
Second edge of write calibration window
found for the selected byte lane (using
dbg_byte_sel). To select a given stage of
Output calibration, use dbg_wrcal_sel_stg, 2'b01
is for byte lanes with a DK clock, and
2'b10 is for byte lanes without a DK
clock.
Final tap setting for write calibration for
the selected byte lane (using
dbg_byte_sel). To select a given stage of
Output calibration, use dbg_wrcal_sel_stg, 2'b01
is for byte lanes with a DK clock, and
2'b10 is for byte lanes without a DK
clock.
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