Xilinx Zynq-7000 User Manual page 75

Table 1-13: Traffic Generator Signal Descriptions (Cont'd)
Signal
vio_instr_mode_value[3:0]
vio_bl_mode_value[3:0]
vio_fixed_instr_value
vio_fixed_bl_value
vio_pause_traffic
vio_data_mask_gen
cmp_data[DWIDTH – 1:0]
cmp_data_valid
cmp_error
error
error_status[n:0]
simple_data0[31:0]
simple_data1[31:0]
simple_data2[31:0]
simple_data3[31:0]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Direction Description
Valid settings for this signal are:
• 0x1: Command type (read/write) as defined by fixed_instr_i.
Input • 0x2: Random read/write commands.
• 0xE: Write only at address zero.
• 0xF: Read only at address zero.
Valid settings for this signal are:
• 0x1: Fixed burst length as defined in the fixed_bl_i inputs.
Input
• 0x2: The user burst length is generated from the internal PRBS
generator. Each burst value defines the number of back-to-back
commands that are generated.
Valid settings are:
Input • 0x0: Write instruction
• 0x1: Read instruction
Input Valid settings are 1 to 256.
Input Pause traffic generation on-the-fly.
This mode is only used if the data mode pattern is address as data.
If this is enabled, a random memc_wr_mask is generated after the
Input memory pattern has been filled in memory. The write data byte
lane is jammed with 8'hFF if the corresponding memc_write_mask
is asserted.
Output Expected data to be compared with read back data from memory.
Output Compare data valid signal.
This compare error flag asserts whenever cmp_data is not the same
Output
as the readback data from memory.
This signal is asserted when the readback data is not equal to the
Output
expected value.
This signal latches these values when the error signal is asserted:
• [31:0]: Read start address
• [37:32]: Read burst length
• [39:38]: Reserved
Output • [40]: mcb_cmd_full
• [41]: mcb_wr_full
• [42]: mcb_rd_empty
• [64 + (DWIDTH – 1):64]: expected_cmp_data
• [64 + (2 × DWIDTH – 1):64 + DWIDTH]: read_data
Input User-defined simple data 0 for simple 8 repeat data pattern.
Input User-defined simple data 1 for simple 8 repeat data pattern.
Input User-defined simple data 2 for simple 8 repeat data pattern.
Input User-defined simple data 3 for simple 8 repeat data pattern.
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