Xilinx Zynq-7000 User Manual page 636

• If used, all termination must be placed as close to the load as possible. The termination
can be placed before or after the load provided that the termination is placed within a
small distance of the load pin. The allowable distance can be determined by simulation.
• The CKE signal should be pulled down during memory initialization with a 4.7 kΩ
resistor connected to GND.
• DM should be pulled to GND if DM is not driven by the FPGA (for scenarios where the
data mask is not used or is disabled).
• LPDDR2 does not have a GUI option to configure the SDRAM output drive strength like
DDR2/DDR3. For LPDDR2, use the default setting of 40Ω for output drive strength.
I/O Standards
These rules apply to the I/O standard selection for LPDDR2 SDRAMs:
• Designs generated by the MIG tool use the HSUL_12 and DIFF_HSUL_12 standards for
all bidirectional I/O (DQ, DQS) in the High-Performance banks.
• The HSUL_12 and DIFF_HSUL_12 standards are used for unidirectional outputs, such as
control/address and forward memory clocks.
Trace Lengths
The trace lengths described in this section are for high-speed operation. The package delay
should be included when determining the effective trace length. Different parts in the same
package have different internal package skew values. Derate the minimum period
appropriately in the MIG Controller Options page when different parts in the same
package are used.
One method to determine the delay is to use the L and C values for each pin from the IBIS
models. The delay value is determined as the square root of (L × C).
Another method is to generate the package lengths using Vivado Design Suite. The
following commands generate a csv file that contains the package delay values for every
pin of the device under consideration.
link_design -part <part_number>
write_csv <file_name>
For example, to obtain the package delay information for the 7 series FPGA
XC7K160T-FF676, this command should be issued:
link_design -part xc7k160tfbg676
write_csv flight_time
This generates a file named flight_time.csv in the current directory with package trace
delay information for each pin. While applying specific trace-matching guidelines for the
LPDDR2 SDRAM interface, this additional package delay term should be considered for the
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
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