Xilinx Zynq-7000 User Manual page 133

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
X-Ref Target - Figure 1-56
Figure 1-56: PHY Block Diagram
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 133
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UG586 November 30, 2016 www.xilinx.com