Xilinx Zynq-7000 User Manual page 501

Debugging the Core
The Debug port is a set of input and output signals that either provide status (outputs) or
allow you to make adjustments as the design is operating (inputs). When generating the
RLDRAM II/RLDRAM 3 design through the MIG tool, an option is provided to turn the
Debug Port ON or OFF. When the Debug port is turned OFF, the outputs of the debug port
are still generated but the inputs are ignored. When the Debug port is turned ON, the
inputs are valid and must be driven to a logical value. Driving the signals incorrectly on the
debug port might cause the design to fail or have less read data capture margin.
When running the core in hardware, a few key signals should be inspected to determine the
status of the design. The dbg_phy_status bus described in
bits for various stages of calibration. Checking the dbg_phy_status bus gives initial
information that can aid in debugging an issue that might arise, determining which portion
of the design to look at, or looking for some common issues.
Table 3-27: Physical Layer Simple Status Bus Description Defined in the rld_phy_top Module
Debug Port Signal Name
dbg_phy_status[0] ~rst_wr_clk
dbg_phy_status[1] po_delay_done
dbg_phy_status[2] init_done
dbg_phy_status[3] rtr_cal_start
dbg_phy_status[4] rtr_cal_done
dbg_phy_status[5] wrcal_start
dbg_phy_status[8:6] dbg_wrcal_done
dbg_phy_status[9] rdlvl_stg1_start
dbg_phy_status[10] rdlvl_cal_done
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Description
FPGA logic reset based on PLL
lock and system input reset
I/O FIFO initialization to
ensure the I/O FIFOs are in an
almost full condition and the
phaser out delay to provide
the 90° phase shift to
address/control signals are
done
RLDRAM II/RLDRAM 3
initialization sequence is
complete
(RLDRAM 3 only) Read training
register stage 1 read
calibration start signal
(RLDRAM 3 only) Read training
register stage 1 read
calibration is complete
Write Calibration start signal
Write Calibration stage
complete
Stage 1 read calibration start
signal
Stage 1 read calibration is
complete
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Table 3-27 consists of status
If Problems Arise
If this signal is deasserted, check
your clock source and system
reset input
Check if the PHY control ready
signal is asserted
(1)
N/A
N/A
N/A
N/A
Check the results of the read
training register stage 1
calibration. See Write
Calibration, page 452.
Check results of write
calibration
N/A
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