Xilinx Zynq-7000 User Manual page 181

Table 1-64: 7 Series FPGA Memory Solution Configuration Parameters (Cont'd)
Parameter
CK_WIDTH
CKE_WIDTH
ODT_WIDTH
COL_WIDTH
RANK_WIDTH
ROW_WIDTH
DM_WIDTH
DQ_WIDTH
DQS_WIDTH
BURST_MODE
BM_CNT_WIDTH
ADDR_CMD_MODE
(3)
ORDERING
STARVE_LIMIT
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
This is the number of CK/CK# outputs to
memory.
This is the number of CKE outputs to memory.
This is the number of ODT outputs to memory.
This is the number of memory column address
bits.
This is the number of bits required to index the
RANK bus.
This is the DRAM component address bus
width.
This is the number of data mask bits.
This is the memory DQ bus width.
This is the memory DQS bus width.
This is the memory data burst length.
This is the number of bits required to index a
bank machine and is given by
ceil(log (nBANK_MACHS)).
2
This parameter is used by the controller to
calculate timing on the memory addr/cmd bus.
This parameter should not be changed.
This option reorders received requests to
optimize data throughput and latency.
This sets the number of times a read request
can lose arbitration before the request declares
itself high priority. The actual number of lost
arbitrations is STARVE_LIMIT × nBANK_MACHS.
www.xilinx.com
Options
This option is based on the selected
MIG tool configuration.
This option is based on the selected
MIG tool configuration.
This option is based on the selected
MIG tool configuration.
This option is based on the selected
memory device.
This parameter value is 1 for both
Single and Dual rank devices.
This option is based on the selected
memory device.
DQ_WIDTH/8
This parameter supports DQ widths
from 8 to a maximum of 72 in
increments of 8. The available
maximum DQ width is frequency
dependent on the selected memory
device.
DQ_WIDTH/8
DDR3: "8"
DDR2: "8"
"1T"
"NORM": Allows the Memory
Controller to reorder read but not
write commands to the memory.
"RELAXED": Allows the Memory
Controller to reorder commands to
the memory for maximum
efficiency. Strong ordering is not
preserved at the native interface in
this mode.
"STRICT": Forces the Memory
Controller to execute commands in
the exact order received.
1, 2, 3, ... 10
Send Feedback
181