Xilinx Zynq-7000 User Manual page 509

Table 3-31: Read Stage 2 Debug Signal Map (Cont'd)
Bits
dbg_stage2_cal[38]
dbg_stage2_cal[127:39]
Write Calibration Debug Map
Table 3-32 indicates the mapping between bits within the dbg_wr_cal bus and debug
signals in the PHY.
Table 3-32: Write Debug Signal Map
Bits PHY Signal Name
dbg_wrcal[3:0] write_cal_cs
dbg_wrcal[4] data_valid_r
dbg_wrcal[5] first_edge_found
dbg_wrcal[6] second_edge_found
dbg_wrcal[7] rdlvl_timeout_error
dbg_wrcal[8] inc_byte_lane_cnt
dbg_wrcal[14:9] po_fine_taps
dbg_wrcal[20:15] po_fine_first_edge
dbg_wrcal[26:21] po_fine_second_edge
dbg_wrcal[27] stg2_eod
dbg_wrcal[28] stg3_eod
dbg_wrcal[37:29] po_counter_read_val
dbg_wrcal[40:38] wrcal_stg
dbg_wrcal[41] record_po_taps
dbg_wrcal[42] data_valid
dbg_wrcal[48:43] wrcal_byte_sel
dbg_wrcal[49] window_valid
dbg_wrcal[54:50] data_valid_cnt
dbg_wrcal[60:55] po_fine_prev_taps
dbg_wrcal[61] first_edge_eod
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
PHY Signal Name
error_adj_latency
Reserved
Description
State machine current state register
Data is valid across data_valid_cnt FPGA logic clock cycles
Flag to indicate first edge is found
Flag to indicate second edge is found
Flag to indicate timeout error to ensure enough time given to
stage 2 edge advanced calibration so you can sample the
results of a given byte lane.
Flag to increment byte lane counter
PHASER_OUT current tap setting
PHASER_OUT first edge tap
PHASER_OUT second edge tap
PHASER_OUT stage 2 end of delay
PHASER_OUT stage 3 end of delay
PHASER_OUT counter value from the PHY
Flag to indicate which stage of write calibration is currently
running
Flag to record a given PHASER_OUT value
Instantaneous data valid check for a given byte lane
Byte lane counter
When first edge and second edge are found, a check is done
to ensure the window is larger than a set size. If too small and
first/second edges cleared, this bit keeps going.
Counter used to check multiple read samples to ensure data is
valid
"Previous" counter to record direction so you know which
direction to move to when an edge found.
First edge not a true edge, hit the limit of the PHASER_OUT
taps
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Description
Indicates error when target PHY_LATENCY cannot be
achieved
Reserved
509
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