Xilinx Zynq-7000 User Manual page 268

Determining If a Data Error is Due to the Write or Read
Determining whether a data error is due to the write or the read can be difficult because if
writes are the cause, read back of data is bad as well. In addition, issues with control or
address timing affect both writes and reads. Some experiments that can help to isolate the
issue are:
• If errors are intermittent, issue a small initial number of writes, followed by continuous
reads from those locations.
• If the reads intermittently yield bad data, there is a potential read issue. If the reads
always yield the same (wrong) data, there is a write issue.
Determine if this is a Write or Read issue using the MIG 7 series Example Design Traffic
Generator within the Vivado logic analyzer feature:
1. Set up all the FIXED parameter values in the RTL:
a. Open example_top.v and change fixed_data_i and fixed_addr_i under the
traffic_gen_top instantiation.
- fixed_addr_i (32'b00000000000000000000000000001000)
- fixed_data_i (32'b11111111111111111111111111111111)
b. Regenerate bitstream.
2. Set the ILA trigger to cmp_error = 1.
3. Set VIO cores to:
vio_modify_enable = 1
vio_pause_traffic = 1
vio_addr_mode_value = 1
vio_bl_mode_value = 1
vio_fixed_bl_value = 8
vio_instr_mode_value = 1
vio_fixed_instr_value = 0 (Write Only)
vio_data_mode_value = 1
vio_pause_traffic = 0
4. Set the VIO cores to:
vio_pause_traffic = 1
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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